[PATCH] D44471: [X86][SSE] Introduce WriteVecMove, WriteVecLoad and WriteVecStore scheduler classes

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86SchedBroadwell.td:122
+def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
+def : WriteRes<WriteVecMove,  [BWPort015]>;
+
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courbet wrote:
> I don't have access to a broadwell to doublecheck, but that does sound weird. I would have expected BWPort5.
MOVAPD/MOVAPS can only use Port5 - MOVDQA can use 015 (search below for MOVDQArr and MOVAPSrr). I can feel a WriteFMove and WriteVecMove coming......


Repository:
  rL LLVM

https://reviews.llvm.org/D44471