[PATCH] D44471: [X86][SSE] Introduce WriteVecMove, WriteVecLoad and WriteVecStore scheduler classes

[Clement Courbet via Phabricator via llvm-commits]

courbet added a comment.

I only checked the Intel sched models.



================
Comment at: lib/Target/X86/X86SchedBroadwell.td:122
+def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
+def : WriteRes<WriteVecMove,  [BWPort015]>;
+
----------------
I don't have access to a broadwell to doublecheck, but that does sound weird. I would have expected BWPort5.


================
Comment at: lib/Target/X86/X86SchedHaswell.td:108
+def : WriteRes<WriteVecLoad,  [HWPort23]> { let Latency = 5; }
+def : WriteRes<WriteVecMove,  [HWPort015]>;
+
----------------
This should be HWPort5


================
Comment at: lib/Target/X86/X86SchedSandyBridge.td:97
+def : WriteRes<WriteVecLoad,  [SBPort23]> { let Latency = 6; }
+def : WriteRes<WriteVecMove,  [SBPort05]>;
+
----------------
This should be SBPort5


================
Comment at: lib/Target/X86/X86SchedSkylakeClient.td:123
+def : WriteRes<WriteVecStore, [SKLPort237, SKLPort4]>;
+def : WriteRes<WriteVecMove,  [SKLPort015]>;
+
----------------
This one is fine.


Repository:
  rL LLVM

https://reviews.llvm.org/D44471