[llvm] r327510 - [X86][Btver2] Fix YMM shuffle, permute and permutevar scheduler costs
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 14 07:05:19 PDT 2018
Author: rksimon
Date: Wed Mar 14 07:05:19 2018
New Revision: 327510
URL: http://llvm.org/viewvc/llvm-project?rev=327510&view=rev
Log:
[X86][Btver2] Fix YMM shuffle, permute and permutevar scheduler costs
Account for ymm double pumping and add proper pshufb/permutevar support
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/test/CodeGen/X86/avx-schedule.ll
llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=327510&r1=327509&r2=327510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Wed Mar 14 07:05:19 2018
@@ -640,6 +640,63 @@ def JWriteVCVTPDYLd: SchedWriteRes<[JLAG
}
def : InstRW<[JWriteVCVTPDYLd, ReadAfterLd], (instrs VCVTPD2DQYrm, VCVTTPD2DQYrm, VCVTPD2PSYrm)>;
+def JWritePSHUFB: SchedWriteRes<[JFPU01]> {
+ let Latency = 2;
+ let ResourceCycles = [4];
+ let NumMicroOps = 3;
+}
+def : InstRW<[JWritePSHUFB], (instrs PSHUFBrr, VPSHUFBrr)>;
+
+def JWritePSHUFBLd: SchedWriteRes<[JLAGU, JFPU01]> {
+ let Latency = 7;
+ let ResourceCycles = [1, 4];
+ let NumMicroOps = 3;
+}
+def : InstRW<[JWritePSHUFBLd, ReadAfterLd], (instrs PSHUFBrm, VPSHUFBrm)>;
+
+def JWriteVPERM: SchedWriteRes<[JFPU01]> {
+ let Latency = 2;
+ let ResourceCycles = [4];
+ let NumMicroOps = 3;
+}
+def : InstRW<[JWriteVPERM], (instrs VPERMILPDrr, VPERMILPSrr)>;
+
+def JWriteVPERMLd: SchedWriteRes<[JLAGU, JFPU01]> {
+ let Latency = 7;
+ let ResourceCycles = [1, 4];
+ let NumMicroOps = 3;
+}
+def : InstRW<[JWriteVPERMLd, ReadAfterLd], (instrs VPERMILPDrm, VPERMILPSrm)>;
+
+def JWriteVPERMY: SchedWriteRes<[JFPU01]> {
+ let Latency = 3;
+ let ResourceCycles = [6];
+ let NumMicroOps = 6;
+}
+def : InstRW<[JWriteVPERMY], (instrs VPERMILPDYrr, VPERMILPSYrr)>;
+
+def JWriteVPERMYLd: SchedWriteRes<[JLAGU, JFPU01]> {
+ let Latency = 8;
+ let ResourceCycles = [1, 6];
+ let NumMicroOps = 6;
+}
+def : InstRW<[JWriteVPERMYLd, ReadAfterLd], (instrs VPERMILPDYrm, VPERMILPSYrm)>;
+
+def JWriteShuffleY: SchedWriteRes<[JFPU01]> {
+ let ResourceCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[JWriteShuffleY], (instrs VMOVDDUPYrr, VMOVSHDUPYrr, VMOVSLDUPYrr,
+ VPERMILPDYri, VPERMILPSYri, VSHUFPDYrri, VSHUFPSYrri)>;
+
+def JWriteShuffleYLd: SchedWriteRes<[JLAGU, JFPU01]> {
+ let Latency = 6;
+ let ResourceCycles = [1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[JWriteShuffleYLd, ReadAfterLd], (instrs VMOVDDUPYrm, VMOVSHDUPYrm, VMOVSLDUPYrm,
+ VPERMILPDYmi, VPERMILPSYmi, VSHUFPDYrmi, VSHUFPSYrmi)>;
+
def JWriteVBlendVPY: SchedWriteRes<[JFPU01]> {
let Latency = 3;
let ResourceCycles = [6];
Modified: llvm/trunk/test/CodeGen/X86/avx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=327510&r1=327509&r2=327510&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-schedule.ll Wed Mar 14 07:05:19 2018
@@ -2691,7 +2691,7 @@ define <4 x double> @test_movddup(<4 x d
; BTVER2-LABEL: test_movddup:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [6:1.00]
-; BTVER2-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:0.50]
+; BTVER2-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:1.00]
; BTVER2-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -3031,7 +3031,7 @@ define <8 x float> @test_movshdup(<8 x f
; BTVER2-LABEL: test_movshdup:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [6:1.00]
-; BTVER2-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:0.50]
+; BTVER2-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:1.00]
; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -3094,7 +3094,7 @@ define <8 x float> @test_movsldup(<8 x f
; BTVER2-LABEL: test_movsldup:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [6:1.00]
-; BTVER2-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:0.50]
+; BTVER2-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:1.00]
; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -3653,7 +3653,7 @@ define <4 x double> @test_permilpd_ymm(<
; BTVER2-LABEL: test_permilpd_ymm:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [6:1.00]
-; BTVER2-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [1:0.50]
+; BTVER2-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [1:1.00]
; BTVER2-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -3779,7 +3779,7 @@ define <8 x float> @test_permilps_ymm(<8
; BTVER2-LABEL: test_permilps_ymm:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [6:1.00]
-; BTVER2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:0.50]
+; BTVER2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]
; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -3835,8 +3835,8 @@ define <2 x double> @test_permilvarpd(<2
;
; BTVER2-LABEL: test_permilvarpd:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
+; BTVER2-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_permilvarpd:
@@ -3891,7 +3891,7 @@ define <4 x double> @test_permilvarpd_ym
; BTVER2-LABEL: test_permilvarpd_ymm:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 # sched: [3:3.00]
-; BTVER2-NEXT: vpermilpd (%rdi), %ymm0, %ymm0 # sched: [6:1.00]
+; BTVER2-NEXT: vpermilpd (%rdi), %ymm0, %ymm0 # sched: [8:3.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_permilvarpd_ymm:
@@ -3945,8 +3945,8 @@ define <4 x float> @test_permilvarps(<4
;
; BTVER2-LABEL: test_permilvarps:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpermilps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT: vpermilps %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
+; BTVER2-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_permilvarps:
@@ -4001,7 +4001,7 @@ define <8 x float> @test_permilvarps_ymm
; BTVER2-LABEL: test_permilvarps_ymm:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vpermilps %ymm1, %ymm0, %ymm0 # sched: [3:3.00]
-; BTVER2-NEXT: vpermilps (%rdi), %ymm0, %ymm0 # sched: [6:1.00]
+; BTVER2-NEXT: vpermilps (%rdi), %ymm0, %ymm0 # sched: [8:3.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_permilvarps_ymm:
@@ -4317,7 +4317,7 @@ define <4 x double> @test_shufpd(<4 x do
;
; BTVER2-LABEL: test_shufpd:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[2],ymm1[3] sched: [1:0.50]
+; BTVER2-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[2],ymm1[3] sched: [1:1.00]
; BTVER2-NEXT: vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [6:1.00]
; BTVER2-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
@@ -4380,7 +4380,7 @@ define <8 x float> @test_shufps(<8 x flo
;
; BTVER2-LABEL: test_shufps:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4] sched: [1:0.50]
+; BTVER2-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4] sched: [1:1.00]
; BTVER2-NEXT: vshufps {{.*#+}} ymm1 = ymm1[0,3],mem[0,0],ymm1[4,7],mem[4,4] sched: [6:1.00]
; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
Modified: llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll?rev=327510&r1=327509&r2=327510&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll Wed Mar 14 07:05:19 2018
@@ -907,8 +907,8 @@ define <16 x i8> @test_pshufb(<16 x i8>
;
; BTVER2-LABEL: test_pshufb:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpshufb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpshufb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT: vpshufb %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
+; BTVER2-NEXT: vpshufb (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_pshufb:
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