[PATCH] D44428: [X86][SSE] Treat (V)MOVAPD/(V)MOVUPD + (V)MOVAPS/(V)MOVUPS reg-reg instructions as moves not shuffles

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D44428#1036105, @courbet wrote:

> In https://reviews.llvm.org/D44428#1036073, @RKSimon wrote:
>
> > I saw this on btver2 - MOVDQA is reported as using JALU0/JALU1 while MOVAPS/MOVAPD reports JFPU0/JFPU1. And it appears to be affecting a couple of other targets with non-exhaustive scheduler model overloads.
>
>
> I see - if there's nothing in common between microarchitectures then ideally shouldn't we avoid putting a default ? I guess what happened here is that someone measured it on Intel and put that here, which ended up hurting btver2... I could see this opposite happening with this change if any intel uarch forgets to override this. Did you check that //all// intel uarchs override this ?


As you can see from the test changes in the patch, these are limited to btver2/znver1/slm/glm - Agner's tables show no diff for pipe usage between dq/ps/pd aligned/unaligned rr moves for these cpus. The tests have pretty much coverage complete for SSE + AVX1/AVX2 cases.

IMO its much safer to default to WriteMove than WriteFShuffle for these instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D44428