[PATCH] D44428: [X86][SSE] Treat (V)MOVAPD/(V)MOVUPD + (V)MOVAPS/(V)MOVUPS reg-reg instructions as moves not shuffles

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

I haven't looked at the sched model details recently, but this seems like a step in the right direction...although we really need:
https://bugs.llvm.org/show_bug.cgi?id=36671 ?

Ie, most reg-reg moves on Zen, IvyBridge or later should be special-cased if we want an accurate simulation.

For example, Agner has this in section 19.13 of the micro-arch doc:
"Register-to-register move instructions are resolved at the register rename stage without using any execution units. 
These instructions have zero latency. It is possible to do six such register renamings per clock cycle, and it is even 
possible to rename the same register several times in one clock cycle."


Repository:
  rL LLVM

https://reviews.llvm.org/D44428