[llvm] r327283 - [X86][Btver2] Use JWriteResFpuPair wrapper for AES/CLMUL/HADD scheduler cases. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Mar 12 08:29:00 2018
New Revision: 327283

URL: http://llvm.org/viewvc/llvm-project?rev=327283&view=rev
Log:
[X86][Btver2] Use JWriteResFpuPair wrapper for AES/CLMUL/HADD scheduler cases. NFCI.

These are single pipe and have the default resource/uop counts like JWriteResFpuPair so there's no need to handle them separately.

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=327283&r1=327282&r2=327283&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Mon Mar 12 08:29:00 2018
@@ -329,52 +329,16 @@ def : WriteRes<WritePCmpEStrILd, [JLAGU,
 // AES Instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WriteAESDecEnc, [JFPU01, JVIMUL]> {
-  let Latency = 3;
-  let ResourceCycles = [1, 1];
-}
-def : WriteRes<WriteAESDecEncLd, [JFPU01, JLAGU, JVIMUL]> {
-  let Latency = 8;
-  let ResourceCycles = [1, 1, 1];
-}
-
-def : WriteRes<WriteAESIMC, [JVIMUL]> {
-  let Latency = 2;
-  let ResourceCycles = [1];
-}
-def : WriteRes<WriteAESIMCLd, [JLAGU, JVIMUL]> {
-  let Latency = 7;
-  let ResourceCycles = [1, 1];
-}
-
-def : WriteRes<WriteAESKeyGen, [JVIMUL]> {
-  let Latency = 2;
-  let ResourceCycles = [1];
-}
-def : WriteRes<WriteAESKeyGenLd, [JLAGU, JVIMUL]> {
-  let Latency = 7;
-  let ResourceCycles = [1, 1];
-}
+defm : JWriteResFpuPair<WriteAESIMC,    JVIMUL, 2>;
+defm : JWriteResFpuPair<WriteAESKeyGen, JVIMUL, 2>;
+defm : JWriteResFpuPair<WriteAESDecEnc, JVIMUL, 3>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Horizontal add/sub  instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WriteFHAdd, [JFPU0]> {
-  let Latency = 3;
-}
-
-def : WriteRes<WriteFHAddLd, [JLAGU, JFPU0]> {
-  let Latency = 8;
-}
-
-def : WriteRes<WritePHAdd, [JFPU01]> {
-  let ResourceCycles = [1];
-}
-def : WriteRes<WritePHAddLd, [JLAGU, JFPU01 ]> {
-  let Latency = 6;
-  let ResourceCycles = [1, 1];
-}
+defm : JWriteResFpuPair<WriteFHAdd,   JFPU0,  3>;
+defm : JWriteResFpuPair<WritePHAdd,   JFPU01, 1>;
 
 def WriteFHAddY: SchedWriteRes<[JFPU0]> {
   let Latency = 3;
@@ -392,14 +356,7 @@ def : InstRW<[WriteFHAddYLd], (instrs VH
 // Carry-less multiplication instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WriteCLMul, [JVIMUL]> {
-  let Latency = 2;
-  let ResourceCycles = [1];
-}
-def : WriteRes<WriteCLMulLd, [JLAGU, JVIMUL]> {
-  let Latency = 7;
-  let ResourceCycles = [1, 1];
-}
+defm : JWriteResFpuPair<WriteCLMul,   JVIMUL, 2>;
 
 // FIXME: pipe for system/microcode?
 def : WriteRes<WriteSystem,     [JAny]> { let Latency = 100; }