[PATCH] D44383: [MC] Move the instruction latency computation from TargetSchedModel to MCSchedModel.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, MatzeB, atrick.

This patch moves the logic that computes the instruction latency from a scheduling class descriptor into MCSchedModel from TargetSchedModel.

The TargetSchedModel API is unchanged; now method `TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &)` simply delegates the latency computation to MCSchedModel.

The goal is to make the latency information accessible through the MCSchedModel interface.
This is particularly important for tools (for example: llvm-mca), that have access to MCSchedModel, but not TargetSchedModel.

This is a first step towards fixing PR36676.

No functional change intended.


https://reviews.llvm.org/D44383

Files:
  include/llvm/MC/MCSchedule.h
  lib/CodeGen/TargetSchedule.cpp
  lib/MC/MCSchedule.cpp


Index: lib/MC/MCSchedule.cpp
===================================================================
--- lib/MC/MCSchedule.cpp
+++ lib/MC/MCSchedule.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include <type_traits>
 
 using namespace llvm;
@@ -32,3 +33,19 @@
                                             0,
                                             0,
                                             nullptr};
+
+int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
+                                      const MCSchedClassDesc &SCDesc) {
+  int Latency = 0;
+  for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
+       DefIdx != DefEnd; ++DefIdx) {
+    // Lookup the definition's write latency in SubtargetInfo.
+    const MCWriteLatencyEntry *WLEntry =
+        STI.getWriteLatencyEntry(&SCDesc, DefIdx);
+    // Early exit if we found an invalid latency.
+    if (WLEntry->Cycles < 0)
+      return WLEntry->Cycles;
+    Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
+  }
+  return Latency;
+}
Index: lib/CodeGen/TargetSchedule.cpp
===================================================================
--- lib/CodeGen/TargetSchedule.cpp
+++ lib/CodeGen/TargetSchedule.cpp
@@ -257,15 +257,7 @@
 
 unsigned
 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
-  unsigned Latency = 0;
-  for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
-       DefIdx != DefEnd; ++DefIdx) {
-    // Lookup the definition's write latency in SubtargetInfo.
-    const MCWriteLatencyEntry *WLEntry =
-      STI->getWriteLatencyEntry(&SCDesc, DefIdx);
-    Latency = std::max(Latency, capLatency(WLEntry->Cycles));
-  }
-  return Latency;
+  return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc));
 }
 
 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
Index: include/llvm/MC/MCSchedule.h
===================================================================
--- include/llvm/MC/MCSchedule.h
+++ include/llvm/MC/MCSchedule.h
@@ -21,6 +21,7 @@
 namespace llvm {
 
 struct InstrItinerary;
+class MCSubtargetInfo;
 
 /// Define a kind of processor resource that will be modeled by the scheduler.
 struct MCProcResourceDesc {
@@ -226,6 +227,10 @@
     return &SchedClassTable[SchedClassIdx];
   }
 
+  /// Returns the latency value for the scheduling class.
+  static int computeInstrLatency(const MCSubtargetInfo &STI,
+                                 const MCSchedClassDesc &SCDesc);
+
   /// Returns the default initialized model.
   static const MCSchedModel &GetDefaultSchedModel() { return Default; }
   static const MCSchedModel Default;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D44383.137997.patch
Type: text/x-patch
Size: 2776 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180312/61261329/attachment.bin>