[PATCH] D44112: TableGen: Type-check BinOps

[Artem Belevich via Phabricator via llvm-commits]

tra accepted this revision.
tra added inline comments.
This revision is now accepted and ready to land.


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Comment at: docs/TableGen/LangIntro.rst:270-271
 
-``!shl(a,b)`` ``!srl(a,b)`` ``!sra(a,b)`` ``!add(a,b)`` ``!and(a,b)``
-    The usual binary and arithmetic operators.
+``!shl(a,b)`` ``!srl(a,b)`` ``!sra(a,b)``
+    The usual shift operators.
+
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We may add few details regarding intended behavior (or lack of guarantees).
I think we should mention that we operate on 64-bit integers and that results of negative shift count or shift overflow is undefined.



Repository:
  rL LLVM

https://reviews.llvm.org/D44112