[PATCH] D44289: [X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, zvi.

We currently avoid inserting these moves during isel in a few cases which is implemented using a whitelist of opcodes. But it's too difficult to generate a perfect list of opcodes to whitelist. Especially with AVX512F without AVX512VL using 512 bit vectors to implement some 128/256 bit operations. Since isel is done bottoms up, we'd have to check the VT and opcode and subtarget in order to determine whether an EXTRACT_SUBREG would be generated for some operations.

So instead of doing that, this patch adds a post processing step that detects when the moves are unnecesssary after isel. At that point any EXTRACT_SUBREGs would have already been created and appear in the DAG. So then we just need to ensure the input to the move isn't one.


https://reviews.llvm.org/D44289

Files:
  lib/Target/X86/X86ISelDAGToDAG.cpp
  lib/Target/X86/X86InstrVecCompiler.td
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/bitcast-setcc-128.ll
  test/CodeGen/X86/merge-consecutive-loads-256.ll
  test/CodeGen/X86/vector-shuffle-variable-256.ll

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