[llvm] r327079 - Propagate flags to SDValue in SplitVecOp_VECREDUCE

[Sameer AbuAsal via llvm-commits]

Author: sabuasal
Date: Thu Mar  8 15:41:40 2018
New Revision: 327079

URL: http://llvm.org/viewvc/llvm-project?rev=327079&view=rev
Log:
Propagate flags to SDValue in SplitVecOp_VECREDUCE

 This patch is a fix for PR36642.

 While legalizing long vector types, make sure the smaller types get the
 flags of the wider type.

 bugzilla link: https://bugs.llvm.org/show_bug.cgi?id=36642

Change-Id: I0c2829639f094c862c10a6b51b342d4c2563e1fa

Added:
    llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=327079&r1=327078&r2=327079&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Mar  8 15:41:40 2018
@@ -1694,8 +1694,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_VEC
 
   // Use the appropriate scalar instruction on the split subvectors before
   // reducing the now partially reduced smaller vector.
-  SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi);
-  return DAG.getNode(N->getOpcode(), dl, ResVT, Partial);
+  SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
+  return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {

Added: llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll?rev=327079&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll Thu Mar  8 15:41:40 2018
@@ -0,0 +1,31 @@
+; REQUIRES: arm-registered-target
+; REQUIRES: asserts
+; RUN: llc %s -debug-only=legalize-types 2>&1 | FileCheck %s
+
+; This test check that when v4f64 gets broken down to two v2f64 it maintains
+; the "nnan" flags.
+
+; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR
+; CHECK-NEXT: Analyzing result type: v4f64
+; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
+
+; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR
+; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR
+; CHECK: Legalizing node: t26: v2f64 = fmaxnum nnan [[VTWO]], [[VTWO]]
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+
+; Function Attrs: norecurse nounwind
+define fastcc double @test() unnamed_addr #1 {
+entry:
+ %0 = insertelement <4 x double> undef, double 1.0, i32 0
+ %1 = insertelement <4 x double> %0, double 1.0, i32 1
+ %2 = insertelement <4 x double> %1, double 1.0, i32 2
+ %3 = insertelement <4 x double> %2, double 1.0, i32 3
+ %4 = call nnan double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double> %3)
+ ret double %4
+}
+
+declare double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double>)