[llvm] r327056 - [llvm-mca] Fix handling of zero-latency instructions.
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 8 12:21:55 PST 2018
Author: adibiagio
Date: Thu Mar 8 12:21:55 2018
New Revision: 327056
URL: http://llvm.org/viewvc/llvm-project?rev=327056&view=rev
Log:
[llvm-mca] Fix handling of zero-latency instructions.
This patch fixes a problem found when testing zero latency instructions on
target AArch64 -mcpu=exynos-m3 / -mcpu=exynos-m1.
On Exynos-m3/m1, direct branches are zero-latency instructions that don't consume
any processor resources. The DispatchUnit marks zero-latency instructions as
"executed", so that no scheduling is required. The event of instruction
executed is then notified to all the listeners, and the reorder buffer (managed
by the RetireControlUnit) is updated. In particular, the entry associated to the
zero-latency instruction in the reorder buffer is marked as executed.
Before this patch, the DispatchUnit forgot to assign a retire control unit token
(RCUToken) to the zero-latency instruction. As a consequence, the RCUToken was
used uninitialized. This was causing a crash in the RetireControlUnit logic.
Fixes PR36650.
Added:
llvm/trunk/test/tools/llvm-mca/AArch64/
llvm/trunk/test/tools/llvm-mca/AArch64/CortexA57/
llvm/trunk/test/tools/llvm-mca/AArch64/CortexA57/direct-branch.s
llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/
llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s
llvm/trunk/test/tools/llvm-mca/AArch64/lit.local.cfg
Modified:
llvm/trunk/tools/llvm-mca/Backend.cpp
llvm/trunk/tools/llvm-mca/Dispatch.cpp
llvm/trunk/tools/llvm-mca/Scheduler.cpp
Added: llvm/trunk/test/tools/llvm-mca/AArch64/CortexA57/direct-branch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/AArch64/CortexA57/direct-branch.s?rev=327056&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/AArch64/CortexA57/direct-branch.s (added)
+++ llvm/trunk/test/tools/llvm-mca/AArch64/CortexA57/direct-branch.s Thu Mar 8 12:21:55 2018
@@ -0,0 +1,61 @@
+# RUN: llvm-mca -march=aarch64 -mcpu=cortex-a57 -iterations=600 -timeline < %s | FileCheck %s
+
+ b t
+
+# CHECK: Iterations: 600
+# CHECK-NEXT: Instructions: 600
+# CHECK-NEXT: Total Cycles: 603
+# CHECK-NEXT: Dispatch Width: 3
+# CHECK-NEXT: IPC: 1.00
+
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 b t
+
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - A57UnitB
+# CHECK-NEXT: [1.0] - A57UnitI
+# CHECK-NEXT: [1.1] - A57UnitI
+# CHECK-NEXT: [2] - A57UnitL
+# CHECK-NEXT: [3] - A57UnitM
+# CHECK-NEXT: [4] - A57UnitS
+# CHECK-NEXT: [5] - A57UnitW
+# CHECK-NEXT: [6] - A57UnitX
+
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
+# CHECK-NEXT: 1.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1.00 - - - - - - - b t
+
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeER . . . b t
+# CHECK: [1,0] D=eER. . . b t
+# CHECK: [2,0] D==eER . . b t
+# CHECK: [3,0] .D==eER . . b t
+
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 10 4.3 4.3 0.0 b t
Added: llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s?rev=327056&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s (added)
+++ llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s Thu Mar 8 12:21:55 2018
@@ -0,0 +1,37 @@
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -iterations=300 -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=M3
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -iterations=300 -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=M1
+
+ b t
+
+# ALL: Iterations: 300
+# ALL-NEXT: Instructions: 300
+
+# M3-NEXT: Total Cycles: 51
+# M3-NEXT: Dispatch Width: 6
+# M3-NEXT: IPC: 5.88
+
+# M1-NEXT: Total Cycles: 76
+# M1-NEXT: Dispatch Width: 4
+# M1-NEXT: IPC: 3.95
+
+
+# ALL: Instruction Info:
+# ALL-NEXT: [1]: #uOps
+# ALL-NEXT: [2]: Latency
+# ALL-NEXT: [3]: RThroughput
+# ALL-NEXT: [4]: MayLoad
+# ALL-NEXT: [5]: MayStore
+# ALL-NEXT: [6]: HasSideEffects
+
+# ALL: [1] [2] [3] [4] [5] [6] Instructions:
+# ALL-NEXT: 1 0 - b t
+
+
+# ALL: Average Wait times (based on the timeline view):
+# ALL-NEXT: [0]: Executions
+# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# ALL-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# ALL: [0] [1] [2] [3]
+# ALL-NEXT: 0. 10 0.0 0.0 0.0 b t
Added: llvm/trunk/test/tools/llvm-mca/AArch64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/AArch64/lit.local.cfg?rev=327056&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/AArch64/lit.local.cfg (added)
+++ llvm/trunk/test/tools/llvm-mca/AArch64/lit.local.cfg Thu Mar 8 12:21:55 2018
@@ -0,0 +1,2 @@
+if not 'AArch64' in config.root.targets:
+ config.unsupported = True
Modified: llvm/trunk/tools/llvm-mca/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Backend.cpp?rev=327056&r1=327055&r2=327056&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Backend.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Backend.cpp Thu Mar 8 12:21:55 2018
@@ -43,11 +43,6 @@ void Backend::runCycle(unsigned Cycle) {
Instructions[IR.first] = std::unique_ptr<Instruction>(NewIS);
NewIS->setRCUTokenID(DU->dispatch(IR.first, NewIS));
- // If this is a zero latency instruction, then we don't need to dispatch
- // it. Instead, we can mark it as executed.
- if (NewIS->isZeroLatency())
- notifyInstructionExecuted(IR.first);
-
// Check if we have dispatched all the instructions.
SM.updateNext();
if (!SM.hasNext())
Modified: llvm/trunk/tools/llvm-mca/Dispatch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Dispatch.cpp?rev=327056&r1=327055&r2=327056&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Dispatch.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Dispatch.cpp Thu Mar 8 12:21:55 2018
@@ -242,6 +242,7 @@ unsigned DispatchUnit::dispatch(unsigned
// Reserve slots in the RCU.
unsigned RCUTokenID = RCU->reserveSlot(IID, NumMicroOps);
+ NewInst->setRCUTokenID(RCUTokenID);
Owner->notifyInstructionDispatched(IID);
SC->scheduleInstruction(IID, NewInst);
Modified: llvm/trunk/tools/llvm-mca/Scheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Scheduler.cpp?rev=327056&r1=327055&r2=327056&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Scheduler.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Scheduler.cpp Thu Mar 8 12:21:55 2018
@@ -264,6 +264,7 @@ Instruction *Scheduler::scheduleInstruct
// eliminated at register renaming stage, since we know in advance that those
// clear their output register.
if (MCIS->isZeroLatency()) {
+ notifyInstructionReady(Idx);
MCIS->forceExecuted();
notifyInstructionIssued(Idx, {});
notifyInstructionExecuted(Idx);
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