[PATCH] D44234: [AArch64] Fix UB about shift amount exceeds data bit-width

[Weiming Zhao via Phabricator via llvm-commits]

weimingz created this revision.
weimingz added a reviewer: eli.friedman.
Herald added subscribers: kristof.beyls, javed.absar, rengolin.

Fixes an UB caught by sanitizer. The shift amount might be larger than 32 so the operand should be 1ULL.
In this patch,  we replace the original expression with  existing API with uint64_t type.


Repository:
  rL LLVM

https://reviews.llvm.org/D44234

Files:
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp


Index: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1512,7 +1512,7 @@
 
   // Because of simplify-demanded-bits in DAGCombine, the mask may have been
   // simplified. Try to undo that
-  AndImm |= (1 << NumberOfIgnoredLowBits) - 1;
+  AndImm |= maskTrailingOnes<uint64_t>(NumberOfIgnoredLowBits);
 
   // The immediate is a mask of the low bits iff imm & (imm+1) == 0
   if (AndImm & (AndImm + 1))


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