[llvm] r326811 - [AArch64] define isExtractSubvectorCheap

[Sebastian Pop via llvm-commits]

The error is due to a missing def-pat for (i64 0)

ISEL: Starting pattern match
  Initial Opcode index to 85068
  Match failed at index 85076
LLVM ERROR: Cannot select: t47: v8i16 = insert_subvector undef:v8i16, t43,
Constant:i64<0>

The code generated from llvm/lib/Target/AArch64/AArch64InstrInfo.td

def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
          (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;

is in ninja/lib/Target/AArch64/AArch64GenDAGISel.inc
At the location of the error it is:
/* 85076*/    OPC_CheckChild2Type, MVT::i32,

And it failed to match the type of operand 2.

adding another def-pat like this fixes it:

def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i64 0)),
          (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;

I will submit a patch.

Sebastian

On Wed, Mar 7, 2018 at 2:50 PM, Sebastian Pop <sebpop at gmail.com> wrote:

> I'm looking at the reduced test.
> Thanks for the heads'up.
>
> On Wed, Mar 7, 2018 at 11:11 AM, David Green <David.Green at arm.com> wrote:
>
>> Hello
>>
>> I believe this is the commit causing this code to fail to compile. It's
>> reduced from some randomised neon code, so sorry if it's a bit ugly.
>> Running with llc claims:
>>
>> error in backend: Cannot select: t47: v8i16 = insert_subvector
>> undef:v8i16, t43,
>>       Constant:i64<0>
>>
>>
>> target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
>> target triple = "aarch64--linux-gnu"
>>
>> @d = common dso_local local_unnamed_addr global <4 x i16>
>> zeroinitializer, align 8
>>
>> define <8 x i16> @c(i32 %e) {
>> entry:
>>   %0 = load <4 x i16>, <4 x i16>* @d, align 8
>>   %vminv = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %0)
>>   %1 = trunc i32 %vminv to i16
>>   %vecinit3 = insertelement <4 x i16> <i16 undef, i16 undef, i16 0, i16
>> 0>, i16 %1, i32 1
>>   %call = tail call <8 x i16> @c(i32 0) #3
>>   %vgetq_lane = extractelement <8 x i16> %call, i32 0
>>   %vset_lane = insertelement <4 x i16> %vecinit3, i16 %vgetq_lane, i32 0
>>   %call4 = tail call i32 bitcast (i32 (...)* @k to i32 (<4 x i16>)*)(<4 x
>> i16> %vset_lane) #3
>>   ret <8 x i16> undef
>> }
>>
>> declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
>> declare i32 @k(...)
>>
>>
>> Any ideas? I'm surprised this isExtractSubvectorCheap would be causing
>> this.
>> Cheers
>> Dave
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>
>
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