[PATCH] D44145: AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:459-460
+
+    unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
+                            AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
+
----------------
nhaehnle wrote:
> What happens if the index operand is in an SGPR?
As implemented today, indirect addressing is only done on VGPRs. Someday we could implement SGPR indexing, but right now the register type of the index doesn't really matter


https://reviews.llvm.org/D44145