[PATCH] D44134: [WebAssembly] Add WebAssemblyException information analysis

[David Majnemer via Phabricator via llvm-commits]

majnemer added inline comments.


================
Comment at: lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp:25-26
+/// Because CFGSort requires all the BBs within a catch part to be sorted
+/// together as it does for loops, this pass calculates the nesting structure of
+/// catch part of exceptions in a function.
+///
----------------
aheejin wrote:
> majnemer wrote:
> > What happens if some BBs belong to two different catch blocks?
> Like loop nesting structure, catch block structure should form a nested structure, so a BB belongs to both catch1 and catch2, catch1 should contain catch2 or vice versa.
This is not so in LLVM IR. For example:


```
define dso_local void @f() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
  invoke void @x0()
          to label %5 unwind label %1

; <label>:1:                                      ; preds = %0
  %2 = landingpad { i8*, i32 }
          catch i8* null
  %3 = extractvalue { i8*, i32 } %2, 0
  %4 = tail call i8* @__cxa_begin_catch(i8* %3) #3
  br label %11

; <label>:5:                                      ; preds = %0
  invoke void @x1()
          to label %10 unwind label %6

; <label>:6:                                      ; preds = %5
  %7 = landingpad { i8*, i32 }
          catch i8* null
  %8 = extractvalue { i8*, i32 } %7, 0
  %9 = tail call i8* @__cxa_begin_catch(i8* %8) #3
  br label %11

; <label>:10:                                     ; preds = %5
  ret void

; <label>:11:                                     ; preds = %6, %1
  tail call void @abort() #4
  unreachable
}

declare dso_local void @x0() local_unnamed_addr #1

declare i32 @__gxx_personality_v0(...)

declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr

declare dso_local void @x1() local_unnamed_addr #1

; Function Attrs: noreturn nounwind
declare dso_local void @abort() local_unnamed_addr #2
```

In this example, BB#11 belongs to two different catch blocks.


Repository:
  rL LLVM

https://reviews.llvm.org/D44134