[PATCH] D44179: [AMDGPU] Widened vector length for global/constant address space.

[Farhana Aleen via Phabricator via llvm-commits]

FarhanaAleen created this revision.
FarhanaAleen added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, arsenm.

GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.

This is a re-submission.


https://reviews.llvm.org/D44179

Files:
  lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
  test/CodeGen/AMDGPU/load-constant-f32.ll
  test/CodeGen/AMDGPU/load-constant-f64.ll
  test/CodeGen/AMDGPU/waitcnt-looptest.ll

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