[PATCH] D44098: [ARM] Relax condition for PerformSHLSimplify

[John Brawn via Phabricator via llvm-commits]

john.brawn added a comment.

It looks like loosening this restriction doesn't necessarily lead to better code being generated, e.g. looking at load_i32_by_i8_bswap in load-combine-big-endian.ll that `lsl r0, r0, #24` introduces a register dependency that wasn't there before which likely makes this worse on an in-order CPU.

Looking at the tests you added it looks like doing this is of benefit when it turns an immediate which can't be encoded (510) into an immediate which can (255), so maybe you should be checking for that? Maybe instead of removing the "is the other operand already a shift" check set a bool, and then later when you know the pre- and post-shift constants only proceed if that bool is false of if the constant is now better.


https://reviews.llvm.org/D44098