[PATCH] D44118: [x86][AArch64] ask the target whether it has a vector blend instruction

[Sebastian Pop via Phabricator via llvm-commits]

sebpop created this revision.
sebpop added reviewers: chandlerc, kristof.beyls, evandro, SjoerdMeijer.
Herald added subscribers: hiraditya, javed.absar, rengolin.

The code to match and produce more x86 vector blends was enabled for all
architectures even though the transform may pessimize the code for other
architectures that do not provide a vector blend instruction.

      

Added an aarch64 testcase to check that a VZIP instruction is generated instead
of byte movs.


Repository:
  rL LLVM

https://reviews.llvm.org/D44118

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/AArch64/aarch64-vuzp.ll
  llvm/test/CodeGen/AArch64/arm64-collect-loh.ll

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