[PATCH] D43973: [AArch64] define isExtractSubvectorCheap

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

It LGTM, but I'd wait a while to give a chance for others to chime up.



================
Comment at: llvm/test/CodeGen/AArch64/arm64-ext.ll:100
-; Essence: a vext is used on %A and something saner than stack load/store for final result.
-define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: test_interleaved:
----------------
Methinks that this test could stay.  Before, it resulted in a mix of `EXT`, `UZP1`, `ZIP1`.  With this patch, in a pair of `LDR`, `TBL`, which seems to be a good result.  Better yet,  were the shuffle index changed to `<i32 4, i32 8, i32 5, i32 9>`, then the result would be just like in the test below.


Repository:
  rL LLVM

https://reviews.llvm.org/D43973