[llvm] r326722 - fix PR36582

[Sebastian Pop via llvm-commits]

Author: spop
Date: Mon Mar  5 09:35:49 2018
New Revision: 326722

URL: http://llvm.org/viewvc/llvm-project?rev=326722&view=rev
Log:
fix PR36582

The error occurs when reading i16 elements (as in the testcase) from a v8i8
with a pattern of <0,2,4,6>. As all the data in the vector is accessed, the
operation is not a VUZP. The patch stops the pattern recognition of VUZP when
EXTRACT_VECTOR_ELT has a different element type than BUILD_VECTOR.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/aarch64-vuzp.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=326722&r1=326721&r2=326722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Mon Mar  5 09:35:49 2018
@@ -6777,11 +6777,17 @@ SDValue AArch64TargetLowering::LowerBUIL
       const SDNode *N = V.getNode();
       if (!isa<ConstantSDNode>(N->getOperand(1)))
         break;
+      SDValue N0 = N->getOperand(0);
 
       // All elements are extracted from the same vector.
-      if (!Vector)
-        Vector = N->getOperand(0).getNode();
-      else if (Vector != N->getOperand(0).getNode()) {
+      if (!Vector) {
+        Vector = N0.getNode();
+        // Check that the type of EXTRACT_VECTOR_ELT matches the type of
+        // BUILD_VECTOR.
+        if (VT.getVectorElementType() !=
+            N0.getValueType().getVectorElementType())
+          break;
+      } else if (Vector != N0.getNode()) {
         Odd = false;
         Even = false;
         break;

Modified: llvm/trunk/test/CodeGen/AArch64/aarch64-vuzp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-vuzp.ll?rev=326722&r1=326721&r2=326722&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/aarch64-vuzp.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/aarch64-vuzp.ll Mon Mar  5 09:35:49 2018
@@ -1,4 +1,6 @@
-; RUN: llc  -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>)
 
 ; CHECK-LABEL: fun1:
 ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
@@ -48,4 +50,15 @@ entry:
   ret i32 undef
 }
 
-declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>)
+; CHECK-LABEL: pr36582:
+; Check that this does not ICE.
+define void @pr36582(i8* %p1, i32* %p2) {
+entry:
+  %x = bitcast i8* %p1 to <8 x i8>*
+  %wide.vec = load <8 x i8>, <8 x i8>* %x, align 1
+  %strided.vec = shufflevector <8 x i8> %wide.vec, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %y = zext <4 x i8> %strided.vec to <4 x i32>
+  %z = bitcast i32* %p2 to <4 x i32>*
+  store <4 x i32> %y, <4 x i32>* %z, align 4
+  ret void
+}