[PATCH] D44031: [X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.

We don't currently reject r8-r15 or xmm8-32 in 32-bit mode.

I think we're probably also missing blocking sil/dil/spl/bpl but that probably requires a different fix strategy.


https://reviews.llvm.org/D44031

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/asm-reject-rex.ll
  test/CodeGen/X86/asm-reject-xmm16.ll


Index: test/CodeGen/X86/asm-reject-xmm16.ll
===================================================================
--- test/CodeGen/X86/asm-reject-xmm16.ll
+++ test/CodeGen/X86/asm-reject-xmm16.ll
@@ -1,5 +1,5 @@
-; RUN: not llc -o /dev/null %s 2>&1 | FileCheck %s
-target triple = "x86_64--"
+; RUN: not llc -o /dev/null %s -mtriple=x86_64-unknown-unknown 2>&1 | FileCheck %s
+; RUN: not llc -o /dev/null %s -mtriple=i386-unknown-unknown -mattr=avx512vl 2>&1 | FileCheck %s
 
 ; CHECK: error: couldn't allocate output register for constraint '{xmm16}'
 define i64 @blup() {
Index: test/CodeGen/X86/asm-reject-rex.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/asm-reject-rex.ll
@@ -0,0 +1,19 @@
+; RUN: not llc -o /dev/null %s -mtriple=i386-unknown-unknown 2>&1 | FileCheck %s
+
+; CHECK: error: couldn't allocate output register for constraint '{xmm8}'
+define i64 @blup() {
+  %v = tail call i64 asm "", "={xmm8},0"(i64 0)
+  ret i64 %v
+}
+
+; CHECK: error: couldn't allocate output register for constraint '{r8d}'
+define i32 @foo() {
+  %v = tail call i32 asm "", "={r8d},0"(i32 0)
+  ret i32 %v
+}
+
+; CHECK: error: couldn't allocate output register for constraint '{rax}'
+define i64 @bar() {
+  %v = tail call i64 asm "", "={rax},0"(i64 0)
+  ret i64 %v
+}
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -39160,6 +39160,16 @@
     return Res;
   }
 
+  // Make sure it isn't a register that requires 64-bit mode.
+  if (!Subtarget.is64Bit() &&
+      (isFRClass(*Res.second) || isGRClass(*Res.second)) &&
+      TRI->getEncodingValue(Res.first) >= 8) {
+    // Register requires REX prefix, but we're in 32-bit mode.
+    Res.first = 0;
+    Res.second = nullptr;
+    return Res;
+  }
+
   // Make sure it isn't a register that requires AVX512.
   if (!Subtarget.hasAVX512() && isFRClass(*Res.second) &&
       TRI->getEncodingValue(Res.first) & 0x10) {


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