[PATCH] D43620: [Pipeliner] Fixed node order issue related to zero latency edges

[Brendon Cahoon via Phabricator via llvm-commits]

bcahoon accepted this revision.
bcahoon added a comment.
This revision is now accepted and ready to land.

Thanks again for the patch to the pipeliner.  I think it looks good, so feel free to commit if you're able to after addressing the final comment.

Thanks,
Brendon



================
Comment at: lib/CodeGen/MachinePipeliner.cpp:937
+  // check for node order issues
+  bool ValidNodeOrder = isValidNodeOrder(Circuits);
+
----------------
Should this call be moved to the DEBUG statement below? If the compiler is built without asserts, then this will generate a warning/error due to an unused variable.


https://reviews.llvm.org/D43620