[PATCH] D43916: Named VReg support for MIR

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi added a comment.

In https://reviews.llvm.org/D43916#1024336, @thegameg wrote:

> Thanks for the patch!
>
> Few remarks:
>
> - The named vregs are not mapped back to the same vreg id. Take this example: ``` --- name:            Proc registers:
>   - { id: 0, class: gpr32, preferred-register: '' } body:             | bb.0: %foo:gpr64 = IMPLICIT_DEF ```
>
>     This will give us this: ``` registers:
>   - { id: 0, class: gpr32, preferred-register: '' }
>   - { id: 1, class: gpr64, preferred-register: '' }
>   - { id: 2, class: gpr64, preferred-register: '' } ```
> - There is no way to specify something like a preferred-register for the named regs, or explicitly force a class on it.
> - Some of the remarks in comments.
>
>   I think it's good approach to keep an unique ID, since it doesn't request much change from MachineRegisterInfo.


I think this could be added in a future patch. I dont think it would be hard to reference a table for the proper pre-allocated vreg. Currently it creates the vreg at parsing time for the named vregs. Does this sound like an ok design for the first version of this patch to you?


Repository:
  rL LLVM

https://reviews.llvm.org/D43916