[llvm] r326500 - [DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 1 14:32:25 PST 2018
Author: ctopper
Date: Thu Mar 1 14:32:25 2018
New Revision: 326500
URL: http://llvm.org/viewvc/llvm-project?rev=326500&view=rev
Log:
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code.
Differential Revision: https://reviews.llvm.org/D42679
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll
llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll
llvm/trunk/test/CodeGen/AArch64/bitfield.ll
llvm/trunk/test/CodeGen/NVPTX/param-load-store.ll
llvm/trunk/test/CodeGen/PowerPC/vec_extract_p9_2.ll
llvm/trunk/test/CodeGen/SystemZ/insert-05.ll
llvm/trunk/test/CodeGen/X86/3addr-or.ll
llvm/trunk/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
llvm/trunk/test/CodeGen/X86/memset-nonzero.ll
llvm/trunk/test/CodeGen/X86/pr27591.ll
llvm/trunk/test/CodeGen/X86/pr35763.ll
llvm/trunk/test/CodeGen/X86/sext-i1.ll
llvm/trunk/test/CodeGen/X86/swift-return.ll
llvm/trunk/test/DebugInfo/X86/sdag-combine.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 1 14:32:25 2018
@@ -7832,7 +7832,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SD
// Try to mask before the extension to avoid having to generate a larger mask,
// possibly over several sub-vectors.
- if (SrcVT.bitsLT(VT)) {
+ if (SrcVT.bitsLT(VT) && VT.isVector()) {
if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
SDValue Op = N0.getOperand(0);
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll Thu Mar 1 14:32:25 2018
@@ -29,11 +29,11 @@ define void @test_stack_slots([8 x i32],
i32 %int, i64 %long) {
%ext_bool = zext i1 %bool to i64
store volatile i64 %ext_bool, i64* @var64, align 8
-; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
-
; Part of last store. Blasted scheduler.
; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32]
+; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
+
; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1
; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
@@ -64,8 +64,8 @@ define void @test_stack_slots([8 x i32],
define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
%ext_bool = zext i1 %bool to i64
store volatile i64 %ext_bool, i64* @var64
-; CHECK: and w[[EXT:[0-9]+]], w0, #0x1
-; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
+; CHECK: and [[EXT:x[0-9]+]], x0, #0x1
+; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
%ext_char = sext i8 %char to i64
store volatile i64 %ext_char, i64* @var64
@@ -74,8 +74,8 @@ define void @test_extension(i1 %bool, i8
%ext_short = zext i16 %short to i64
store volatile i64 %ext_short, i64* @var64
-; CHECK: and w[[EXT:[0-9]+]], w2, #0xffff
-; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
+; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff
+; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
%ext_int = zext i32 %int to i64
store volatile i64 %ext_int, i64* @var64
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-arith.ll Thu Mar 1 14:32:25 2018
@@ -123,8 +123,7 @@ entry:
define i64 @t14(i16 %a, i64 %x) nounwind ssp {
entry:
; CHECK-LABEL: t14:
-; CHECK: and w8, w0, #0xffff
-; CHECK: add x0, x1, w8, uxtw #3
+; CHECK: add x0, x1, w0, uxth #3
; CHECK: ret
%c = zext i16 %a to i64
%d = shl i64 %c, 3
Modified: llvm/trunk/test/CodeGen/AArch64/bitfield.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bitfield.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/bitfield.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/bitfield.ll Thu Mar 1 14:32:25 2018
@@ -31,7 +31,7 @@ define void @test_extendb64(i8 %var) {
; correct.
%uxt64 = zext i8 %var to i64
store volatile i64 %uxt64, i64* @var64
-; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xff
+; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xff
ret void
}
@@ -63,7 +63,7 @@ define void @test_extendh64(i16 %var) {
; correct.
%uxt64 = zext i16 %var to i64
store volatile i64 %uxt64, i64* @var64
-; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff
+; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffff
ret void
}
Modified: llvm/trunk/test/CodeGen/NVPTX/param-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/param-load-store.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/param-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/param-load-store.ll Thu Mar 1 14:32:25 2018
@@ -25,9 +25,11 @@
; CHECK-NEXT: .param .b32 test_i1_param_0
; CHECK: ld.param.u8 [[A8:%rs[0-9]+]], [test_i1_param_0];
; CHECK: and.b16 [[A:%rs[0-9]+]], [[A8]], 1;
-; CHECK: cvt.u32.u16 [[B:%r[0-9]+]], [[A]]
+; CHECK: setp.eq.b16 %p1, [[A]], 1
+; CHECK: cvt.u32.u16 [[B:%r[0-9]+]], [[A8]]
+; CHECK: and.b32 [[C:%r[0-9]+]], [[B]], 1;
; CHECK: .param .b32 param0;
-; CHECK: st.param.b32 [param0+0], [[B]]
+; CHECK: st.param.b32 [param0+0], [[C]]
; CHECK: .param .b32 retval0;
; CHECK: call.uni
; CHECK-NEXT: test_i1,
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_extract_p9_2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_extract_p9_2.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_extract_p9_2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_extract_p9_2.ll Thu Mar 1 14:32:25 2018
@@ -7,13 +7,13 @@ define zeroext i8 @test_add1(<16 x i8> %
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextubrx 3, 5, 2
; CHECK-LE-NEXT: add 3, 3, 6
-; CHECK-LE-NEXT: rlwinm 3, 3, 0, 24, 31
+; CHECK-LE-NEXT: clrldi 3, 3, 56
; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add1:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vextublx 3, 5, 2
; CHECK-BE-NEXT: add 3, 3, 6
-; CHECK-BE-NEXT: rlwinm 3, 3, 0, 24, 31
+; CHECK-BE-NEXT: clrldi 3, 3, 56
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %a, i32 %index
@@ -52,14 +52,14 @@ define zeroext i16 @test_add3(<8 x i16>
; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
; CHECK-LE-NEXT: vextuhrx 3, 3, 2
; CHECK-LE-NEXT: add 3, 3, 6
-; CHECK-LE-NEXT: rlwinm 3, 3, 0, 16, 31
+; CHECK-LE-NEXT: clrldi 3, 3, 48
; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add3:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
; CHECK-BE-NEXT: vextuhlx 3, 3, 2
; CHECK-BE-NEXT: add 3, 3, 6
-; CHECK-BE-NEXT: rlwinm 3, 3, 0, 16, 31
+; CHECK-BE-NEXT: clrldi 3, 3, 48
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %a, i32 %index
Modified: llvm/trunk/test/CodeGen/SystemZ/insert-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/insert-05.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/insert-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/insert-05.ll Thu Mar 1 14:32:25 2018
@@ -214,8 +214,8 @@ define i64 @f18(i32 %a) {
; The truncation here isn't free; we need an explicit zero extension.
define i64 @f19(i32 %a) {
; CHECK-LABEL: f19:
-; CHECK: llcr %r2, %r2
-; CHECK: iihf %r2, 1
+; CHECK: llgcr %r2, %r2
+; CHECK: oihl %r2, 1
; CHECK: br %r14
%trunc = trunc i32 %a to i8
%ext = zext i8 %trunc to i64
Modified: llvm/trunk/test/CodeGen/X86/3addr-or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/3addr-or.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/3addr-or.ll (original)
+++ llvm/trunk/test/CodeGen/X86/3addr-or.ll Thu Mar 1 14:32:25 2018
@@ -20,6 +20,7 @@ define i32 @test1(i32 %x) nounwind ssp {
define i64 @test2(i8 %A, i8 %B) nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: shll $4, %edi
; CHECK-NEXT: andl $48, %edi
Modified: llvm/trunk/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll Thu Mar 1 14:32:25 2018
@@ -60,6 +60,7 @@ declare <16 x i32> @llvm.x86.avx512.broa
define <8 x i64> @test_x86_broadcastmb_512(i8 %a0) {
; CHECK-LABEL: test_x86_broadcastmb_512:
; CHECK: ## %bb.0:
+; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: vpbroadcastq %rax, %zmm0
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll Thu Mar 1 14:32:25 2018
@@ -94,6 +94,7 @@ declare <4 x i32> @llvm.x86.avx512.broad
define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) {
; CHECK-LABEL: test_x86_broadcastmb_256:
; CHECK: ## %bb.0:
+; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: vpbroadcastq %rax, %ymm0
; CHECK-NEXT: retq
@@ -105,6 +106,7 @@ declare <4 x i64> @llvm.x86.avx512.broad
define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) {
; CHECK-LABEL: test_x86_broadcastmb_128:
; CHECK: ## %bb.0:
+; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: vpbroadcastq %rax, %xmm0
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll Thu Mar 1 14:32:25 2018
@@ -2707,8 +2707,7 @@ define zeroext i4 @test_vpcmpeqq_v2i1_v4
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -2735,8 +2734,7 @@ define zeroext i4 @test_vpcmpeqq_v2i1_v4
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -2766,8 +2764,7 @@ define zeroext i4 @test_masked_vpcmpeqq_
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -2799,8 +2796,7 @@ define zeroext i4 @test_masked_vpcmpeqq_
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -2832,8 +2828,7 @@ define zeroext i4 @test_vpcmpeqq_v2i1_v4
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -2864,8 +2859,7 @@ define zeroext i4 @test_masked_vpcmpeqq_
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -7596,8 +7590,7 @@ define zeroext i4 @test_vpcmpsgtq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -7624,8 +7617,7 @@ define zeroext i4 @test_vpcmpsgtq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -7655,8 +7647,7 @@ define zeroext i4 @test_masked_vpcmpsgtq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -7688,8 +7679,7 @@ define zeroext i4 @test_masked_vpcmpsgtq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -7721,8 +7711,7 @@ define zeroext i4 @test_vpcmpsgtq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -7753,8 +7742,7 @@ define zeroext i4 @test_masked_vpcmpsgtq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -12589,8 +12577,7 @@ define zeroext i4 @test_vpcmpsgeq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -12617,8 +12604,7 @@ define zeroext i4 @test_vpcmpsgeq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -12648,8 +12634,7 @@ define zeroext i4 @test_masked_vpcmpsgeq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -12681,8 +12666,7 @@ define zeroext i4 @test_masked_vpcmpsgeq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -12714,8 +12698,7 @@ define zeroext i4 @test_vpcmpsgeq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -12746,8 +12729,7 @@ define zeroext i4 @test_masked_vpcmpsgeq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17602,8 +17584,7 @@ define zeroext i4 @test_vpcmpultq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17630,8 +17611,7 @@ define zeroext i4 @test_vpcmpultq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17661,8 +17641,7 @@ define zeroext i4 @test_masked_vpcmpultq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17694,8 +17673,7 @@ define zeroext i4 @test_masked_vpcmpultq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17727,8 +17705,7 @@ define zeroext i4 @test_vpcmpultq_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -17759,8 +17736,7 @@ define zeroext i4 @test_masked_vpcmpultq
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21519,8 +21495,7 @@ define zeroext i4 @test_vcmpoeqpd_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21547,8 +21522,7 @@ define zeroext i4 @test_vcmpoeqpd_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21576,8 +21550,7 @@ define zeroext i4 @test_vcmpoeqpd_v2i1_v
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21608,8 +21581,7 @@ define zeroext i4 @test_masked_vcmpoeqpd
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21640,8 +21612,7 @@ define zeroext i4 @test_masked_vcmpoeqpd
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
@@ -21673,8 +21644,7 @@ define zeroext i4 @test_masked_vcmpoeqpd
; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax
-; NoVLX-NEXT: andb $3, %al
-; NoVLX-NEXT: movzbl %al, %eax
+; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/memset-nonzero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memset-nonzero.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/memset-nonzero.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memset-nonzero.ll Thu Mar 1 14:32:25 2018
@@ -195,6 +195,7 @@ declare i8* @__memset_chk(i8*, i32, i64,
define void @memset_16_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_16_nonconst_bytes:
; SSE: # %bb.0:
+; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
@@ -232,6 +233,7 @@ define void @memset_16_nonconst_bytes(i8
define void @memset_32_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_32_nonconst_bytes:
; SSE: # %bb.0:
+; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
@@ -275,6 +277,7 @@ define void @memset_32_nonconst_bytes(i8
define void @memset_64_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_64_nonconst_bytes:
; SSE: # %bb.0:
+; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
@@ -326,6 +329,7 @@ define void @memset_64_nonconst_bytes(i8
define void @memset_128_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_128_nonconst_bytes:
; SSE: # %bb.0:
+; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx
Modified: llvm/trunk/test/CodeGen/X86/pr27591.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr27591.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr27591.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr27591.ll Thu Mar 1 14:32:25 2018
@@ -9,8 +9,8 @@ define void @test1(i32 %x) #0 {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: cmpl $0, %edi
; CHECK-NEXT: setne %al
-; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %edi
+; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: callq callee1
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/pr35763.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr35763.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr35763.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr35763.ll Thu Mar 1 14:32:25 2018
@@ -10,10 +10,10 @@
define void @PR35763() {
; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
-; CHECK-NEXT: movzwl z+{{.*}}(%rip), %ecx
-; CHECK-NEXT: orl %eax, %ecx
-; CHECK-NEXT: movq %rcx, {{.*}}(%rip)
+; CHECK-NEXT: movl {{.*}}(%rip), %eax
+; CHECK-NEXT: orl z+{{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl %ax, %eax
+; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movl z+{{.*}}(%rip), %eax
; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx
; CHECK-NEXT: shlq $32, %rcx
Modified: llvm/trunk/test/CodeGen/X86/sext-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-i1.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sext-i1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sext-i1.ll Thu Mar 1 14:32:25 2018
@@ -157,9 +157,8 @@ define i32 @select_0_or_1s_zeroext(i1 ze
define i32 @select_0_or_1s_signext(i1 signext %cond) {
; X32-LABEL: select_0_or_1s_signext:
; X32: # %bb.0:
-; X32-NEXT: movb {{[0-9]+}}(%esp), %al
-; X32-NEXT: andb $1, %al
-; X32-NEXT: movzbl %al, %eax
+; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: andl $1, %eax
; X32-NEXT: decl %eax
; X32-NEXT: retl
;
Modified: llvm/trunk/test/CodeGen/X86/swift-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/swift-return.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/swift-return.ll (original)
+++ llvm/trunk/test/CodeGen/X86/swift-return.ll Thu Mar 1 14:32:25 2018
@@ -233,17 +233,17 @@ define void @consume_i1_ret() {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq produce_i1_ret
-; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip)
-; CHECK-NEXT: andb $1, %dl
; CHECK-NEXT: movzbl %dl, %eax
+; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip)
-; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %eax
+; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip)
-; CHECK-NEXT: andb $1, %r8b
; CHECK-NEXT: movzbl %r8b, %eax
+; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip)
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
Modified: llvm/trunk/test/DebugInfo/X86/sdag-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/sdag-combine.ll?rev=326500&r1=326499&r2=326500&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/sdag-combine.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/sdag-combine.ll Thu Mar 1 14:32:25 2018
@@ -15,7 +15,7 @@ define swiftcc void @g() #0 !dbg !5 {
entry:
%0 = alloca %TSb, align 1
%1 = call swiftcc i1 @f(), !dbg !7
- ; CHECK: DBG_VALUE debug-use $rax, debug-use $noreg, !8, !DIExpression(), debug-location !7
+ ; CHECK: DBG_VALUE debug-use $rcx, debug-use $noreg, !8, !DIExpression(), debug-location !7
call void @llvm.dbg.value(metadata i1 %1, metadata !8, metadata !DIExpression()), !dbg !7
%2 = getelementptr inbounds %TSb, %TSb* %0, i32 0, i32 0, !dbg !7
store i1 %1, i1* %2, align 1, !dbg !7
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