[llvm] r326492 - [Hexagon] Add trap1 instruction
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 1 13:54:09 PST 2018
Author: kparzysz
Date: Thu Mar 1 13:54:08 2018
New Revision: 326492
URL: http://llvm.org/viewvc/llvm-project?rev=326492&view=rev
Log:
[Hexagon] Add trap1 instruction
Added:
llvm/trunk/test/MC/Hexagon/J2_trap1_dep.s
Modified:
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td
llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td
llvm/trunk/test/MC/Hexagon/instructions/system_user.s
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=326492&r1=326491&r2=326492&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Thu Mar 1 13:54:08 2018
@@ -1333,6 +1333,17 @@ int HexagonAsmParser::processInstruction
}
break;
+ case Hexagon::J2_trap1:
+ if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
+ MCOperand &Rx = Inst.getOperand(0);
+ MCOperand &Ry = Inst.getOperand(1);
+ if (Rx.getReg() != Hexagon::R0 || Ry.getReg() != Hexagon::R0) {
+ Error(IDLoc, "trap1 can only have register r0 as operand");
+ return Match_InvalidOperand;
+ }
+ }
+ break;
+
case Hexagon::A2_iconst: {
Inst.setOpcode(Hexagon::A2_addi);
MCOperand Reg = Inst.getOperand(0);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td?rev=326492&r1=326491&r2=326492&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td Thu Mar 1 13:54:08 2018
@@ -79,6 +79,7 @@ def tc_55050d58 : InstrItinClass;
def tc_56d25411 : InstrItinClass;
def tc_57288781 : InstrItinClass;
def tc_594ab548 : InstrItinClass;
+def tc_59a01ead : InstrItinClass;
def tc_5acef64a : InstrItinClass;
def tc_5ba5997d : InstrItinClass;
def tc_5eb851fc : InstrItinClass;
@@ -263,6 +264,7 @@ class DepScalarItinV4 {
InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>,
InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_59a01ead, [InstrStage<1, [SLOT2]>]>,
InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>,
@@ -448,6 +450,7 @@ class DepScalarItinV5 {
InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>,
InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_59a01ead, [InstrStage<1, [SLOT2]>]>,
InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>,
@@ -840,6 +843,10 @@ class DepScalarItinV55 {
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_59a01ead, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5acef64a, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1568,6 +1575,10 @@ class DepScalarItinV60 {
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_59a01ead, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5acef64a, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -2311,6 +2322,11 @@ class DepScalarItinV60se {
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_59a01ead, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5acef64a, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -3057,6 +3073,10 @@ class DepScalarItinV62 {
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_59a01ead, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5acef64a, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -3785,6 +3805,10 @@ class DepScalarItinV65 {
[InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_59a01ead, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5acef64a, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td?rev=326492&r1=326491&r2=326492&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td Thu Mar 1 13:54:08 2018
@@ -5669,6 +5669,30 @@ let Inst{13-13} = 0b0;
let Inst{31-16} = 0b0101010000000000;
let isSolo = 1;
}
+def J2_trap1 : HInst<
+(outs IntRegs:$Rx32),
+(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
+"trap1($Rx32,#$Ii)",
+tc_59a01ead, TypeJ>, Enc_33f8ba {
+let Inst{1-0} = 0b00;
+let Inst{7-5} = 0b000;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b01010100100;
+let hasNewValue = 1;
+let opNewValue = 0;
+let isSolo = 1;
+let Uses = [GOSP];
+let Defs = [GOSP, PC];
+let Constraints = "$Rx32 = $Rx32in";
+}
+def J2_trap1_noregmap : HInst<
+(outs),
+(ins u8_0Imm:$Ii),
+"trap1(#$Ii)",
+tc_59a01ead, TypeMAPPING> {
+let isPseudo = 1;
+let isCodeGenOnly = 1;
+}
def J4_cmpeq_f_jumpnv_nt : HInst<
(outs),
(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td?rev=326492&r1=326491&r2=326492&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td Thu Mar 1 13:54:08 2018
@@ -26,6 +26,7 @@ def J2_jumpf_nopred_mapAlias : InstAlias
def J2_jumprf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>;
def J2_jumprt_nopred_mapAlias : InstAlias<"if ($Pu4) jumpr $Rs32", (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32)>;
def J2_jumpt_nopred_mapAlias : InstAlias<"if ($Pu4) jump $Ii", (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii)>;
+def J2_trap1_noregmapAlias : InstAlias<"trap1(#$Ii)", (J2_trap1 R0, u8_0Imm:$Ii)>;
def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32 = memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32 = memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32 = membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
Added: llvm/trunk/test/MC/Hexagon/J2_trap1_dep.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/J2_trap1_dep.s?rev=326492&view=auto
==============================================================================
--- llvm/trunk/test/MC/Hexagon/J2_trap1_dep.s (added)
+++ llvm/trunk/test/MC/Hexagon/J2_trap1_dep.s Thu Mar 1 13:54:08 2018
@@ -0,0 +1,6 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V65
+
+# CHECK-V62: trap1(r0,#0)
+# CHECK-V65: trap1(r0,#0)
+trap1(#0)
Modified: llvm/trunk/test/MC/Hexagon/instructions/system_user.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/system_user.s?rev=326492&r1=326491&r2=326492&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/instructions/system_user.s (original)
+++ llvm/trunk/test/MC/Hexagon/instructions/system_user.s Thu Mar 1 13:54:08 2018
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv65 -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
# Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER
# Load locked
@@ -57,3 +57,9 @@ syncht
# CHECK: 18 df 00 54
trap0(#254)
+
+# CHECK: 14 df 80 54
+trap1(r0, #253)
+
+# CHECK: 14 df 80 54
+trap1(#253)
More information about the llvm-commits
mailing list