[llvm] r326479 - AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 1 12:40:55 PST 2018 

Author: arsenm
Date: Thu Mar  1 12:40:55 2018
New Revision: 326479

URL: http://llvm.org/viewvc/llvm-project?rev=326479&view=rev
Log:
AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr

Patch by Tom Stellard

Added:
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=326479&r1=326478&r2=326479&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Thu Mar  1 12:40:55 2018
@@ -286,9 +286,22 @@ AMDGPURegisterBankInfo::getInstrMapping(
     break;
   }
   case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
-    unsigned IntrinsicID = MI.getOperand(0).getIntrinsicID();
-    switch (IntrinsicID) {
-    case Intrinsic::amdgcn_exp: {
+    switch (MI.getOperand(0).getIntrinsicID()) {
+    default:
+      return getInvalidInstructionMapping();
+    case Intrinsic::amdgcn_exp_compr:
+      OpdsMapping[0] = nullptr; // IntrinsicID
+      // FIXME: These are immediate values which can't be read from registers.
+      OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
+      OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
+      // FIXME: Could we support packed types here?
+      OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
+      OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
+      // FIXME: These are immediate values which can't be read from registers.
+      OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
+      OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
+      break;
+    case Intrinsic::amdgcn_exp:
       OpdsMapping[0] = nullptr; // IntrinsicID
       // FIXME: These are immediate values which can't be read from registers.
       OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
@@ -303,7 +316,6 @@ AMDGPURegisterBankInfo::getInstrMapping(
       OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
       break;
     }
-    }
     break;
   }
   case AMDGPU::G_LOAD:

Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir?rev=326479&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir Thu Mar  1 12:40:55 2018
@@ -0,0 +1,67 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+--- |
+  define void @exp_compr_v2f16_s() {
+    call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0)
+    ret void
+  }
+  define void @exp_compr_v2f16_v() {
+    call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0)
+    ret void
+  }
+
+  declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1)
+  declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1)
+
+...
+
+---
+name: exp_compr_v2f16_s
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+    ; CHECK-LABEL: name: exp_compr_v2f16_s
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
+    ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
+    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[C2]](s1), [[C3]](s1)
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s32) = COPY $sgpr0
+    %3:_(s32) = COPY $sgpr1
+    %6:_(s1) = G_CONSTANT i1 0
+    %7:_(s1) = G_CONSTANT i1 0
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
+...
+---
+name: exp_compr_v2f16_v
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+    ; CHECK-LABEL: name: exp_compr_v2f16_v
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
+    ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
+    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY]](s32), [[COPY1]](s32), [[C2]](s1), [[C3]](s1)
+    %0:_(s32) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s32) = COPY $vgpr0
+    %3:_(s32) = COPY $vgpr1
+    %6:_(s1) = G_CONSTANT i1 0
+    %7:_(s1) = G_CONSTANT i1 0
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
+...

More information about the llvm-commits mailing list