[PATCH] D43903: [AArch64] generate vuzp instead of mov

[Sebastian Pop via Phabricator via llvm-commits]

sebpop created this revision.
sebpop added reviewers: SjoerdMeijer, t.p.northover.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar, rengolin.

when a BUILD_VECTOR is created out of a sequence of EXTRACT_VECTOR_ELT with a
 specific pattern sequence, either <0, 2, 4, ...> or <1, 3, 5, ...>, replace the
 BUILD_VECTOR with either vuzp1 or vuzp2.

With this patch LLVM generates the following code for the first function fun1 in the testcase:
	adrp	x8, .LCPI0_0
	ldr	q0, [x8, :lo12:.LCPI0_0]
	tbl	v0.16b, { v0.16b }, v0.16b
	ext	v1.16b, v0.16b, v0.16b, #8
	uzp1	v0.8b, v0.8b, v1.8b
	str	d0, [x8]
ret

Without this patch LLVM currently generates this code:
	adrp	x8, .LCPI0_0
	ldr	q0, [x8, :lo12:.LCPI0_0]
	tbl	v0.16b, { v0.16b }, v0.16b
	mov	v1.16b, v0.16b
	mov	v1.b[1], v0.b[2]
	mov	v1.b[2], v0.b[4]
	mov	v1.b[3], v0.b[6]
	mov	v1.b[4], v0.b[8]
	mov	v1.b[5], v0.b[10]
	mov	v1.b[6], v0.b[12]
	mov	v1.b[7], v0.b[14]
	str	d1, [x8]
ret


Repository:
  rL LLVM

https://reviews.llvm.org/D43903

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-vuzp.ll

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