[llvm] r326262 - [Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Feb 27 14:40:52 2018
New Revision: 326262

URL: http://llvm.org/viewvc/llvm-project?rev=326262&view=rev
Log:
[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX

Absence of memory operands is treated as "aliasing everything", so
dropping them is sufficient.

Recommit r326256 with a fixed testcase.

Modified:
    llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
    llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll

Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=326262&r1=326261&r2=326262&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Tue Feb 27 14:40:52 2018
@@ -3099,8 +3099,10 @@ void SwingSchedulerDAG::updateMemOperand
       int64_t AdjOffset = Delta * Num;
       NewMemRefs[Refs++] =
           MF.getMachineMemOperand(MMO, AdjOffset, MMO->getSize());
-    } else
-      NewMemRefs[Refs++] = MF.getMachineMemOperand(MMO, 0, UINT64_MAX);
+    } else {
+      NewMI.dropMemRefs();
+      return;
+    }
   }
   NewMI.setMemRefs(NewMemRefs, NewMemRefs + NumRefs);
 }

Modified: llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll?rev=326262&r1=326261&r2=326262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll Tue Feb 27 14:40:52 2018
@@ -6,14 +6,14 @@
 ; CHECK: = and
 ; CHECK: = and
 ; CHECK: = and
-; CHECK: [[REG0:(r[0-9]+)]] = and([[REG1:(r[0-9]+)]],#255)
-; CHECK-NOT: [[REG0]] = and([[REG1]],#255)
+; CHECK: r[[REG0:[0-9]+]] = and(r[[REG1:[0-9]+]],#255)
+; CHECK-NOT: r[[REG0]] = and(r[[REG1]],#255)
 ; CHECK: loop0(.LBB0_[[LOOP:.]],
 ; CHECK: .LBB0_[[LOOP]]:
-; CHECK: [[REG0]] += add
-; CHECK: [[REG2:r[0-9]+]] = and
+; CHECK: r[[REG0]] += add
 ; CHECK: = and
-; CHECK: [[REG0]] = [[REG2]]
+; CHECK: r[[REG2:[0-9]+]] = and
+; CHECK: r[[REG0]]{{:[0-9]+}} = combine(r[[REG2]],{{r[0-9]+}})
 ; CHECK: endloop
 
 ; Function Attrs: nounwind