[PATCH] D43807: ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.

[Peter Collingbourne via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL326226: ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR. (authored by pcc, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43807?vs=136035&id=136110#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43807

Files:
  llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/trunk/test/CodeGen/Thumb2/cmp-frame.ll


Index: llvm/trunk/test/CodeGen/Thumb2/cmp-frame.ll
===================================================================
--- llvm/trunk/test/CodeGen/Thumb2/cmp-frame.ll
+++ llvm/trunk/test/CodeGen/Thumb2/cmp-frame.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "thumbv7-linux-androideabi"
+
+define i1 @f() {
+  %a = alloca i8*
+  ; CHECK: adds.w r0, sp, #0
+  ; CHECK: it ne
+  %cmp = icmp ne i8** %a, null
+  ret i1 %cmp
+}
Index: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -489,7 +489,8 @@
     Offset += MI.getOperand(FrameRegIdx+1).getImm();
 
     unsigned PredReg;
-    if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) {
+    if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
+        !MI.definesRegister(ARM::CPSR)) {
       // Turn it into a move.
       MI.setDesc(TII.get(ARM::tMOVr));
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);


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