[llvm] r326220 - [Hexagon] Add patterns for compares of i1 values

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Feb 27 10:31:46 2018
New Revision: 326220

URL: http://llvm.org/viewvc/llvm-project?rev=326220&view=rev
Log:
[Hexagon] Add patterns for compares of i1 values

Added:
    llvm/trunk/test/CodeGen/Hexagon/isel-setcc-i1.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=326220&r1=326219&r2=326220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Tue Feb 27 10:31:46 2018
@@ -679,8 +679,10 @@ def: Pat<(i32 (zext (i1 (seteq I32:$Rs,
 def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
          (A4_rcmpneqi I32:$Rs, imm:$s8)>;
 
-def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),
-         (C2_xor I1:$Ps, I1:$Pt)>;
+def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>;
+def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>;
+def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)),  (C2_xor I1:$Ps, (C2_not I1:$Pt))>;
+def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),  (C2_xor I1:$Ps, I1:$Pt)>;
 
 def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
          (A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>;

Added: llvm/trunk/test/CodeGen/Hexagon/isel-setcc-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/isel-setcc-i1.ll?rev=326220&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/isel-setcc-i1.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/isel-setcc-i1.ll Tue Feb 27 10:31:46 2018
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that this compiles successfully.
+; CHECK: if (p0)
+
+target triple = "hexagon"
+
+define void @fred() #0 {
+b0:
+  br label %b1
+
+b1:                                               ; preds = %b1, %b0
+  %v2 = load i32, i32* undef, align 4
+  %v3 = select i1 undef, i32 %v2, i32 0
+  %v4 = and i32 %v3, 7
+  %v5 = icmp eq i32 %v4, 4
+  %v6 = or i1 undef, %v5
+  %v7 = and i1 undef, %v6
+  %v8 = xor i1 %v7, true
+  %v9 = or i1 undef, %v8
+  br i1 %v9, label %b10, label %b1
+
+b10:                                              ; preds = %b1
+  unreachable
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv55" }