[PATCH] D42838: [AMDGPU] added writelane intrinsic

[Tim Renouf via Phabricator via llvm-commits]

tpr updated this revision to Diff 135922.
tpr added a comment.

V4: Mark the input undef only on the first sgpr spill in the first basic

  block for that vgpr. Added the suggested two tests.


Repository:
  rL LLVM

https://reviews.llvm.org/D42838

Files:
  include/llvm/IR/IntrinsicsAMDGPU.td
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.h
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/VOP2Instructions.td
  test/CodeGen/AMDGPU/byval-frame-setup.ll
  test/CodeGen/AMDGPU/callee-frame-setup.ll
  test/CodeGen/AMDGPU/inserted-wait-states.mir
  test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
  test/CodeGen/AMDGPU/sibling-call.ll

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