[llvm] r326094 - [CodeGen] Don't omit any redundant information in -debug output
Francis Visoiu Mistrih via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 26 07:23:42 PST 2018
Author: thegameg
Date: Mon Feb 26 07:23:42 2018
New Revision: 326094
URL: http://llvm.org/viewvc/llvm-project?rev=326094&view=rev
Log:
[CodeGen] Don't omit any redundant information in -debug output
In r322867, we introduced IsStandalone when printing MIR in -debug
output. The default behaviour for that was:
1) If any of MBB, MI, or MO are -debug-printed separately, don't omit any
redundant information.
2) When -debug-printing a MF entirely, don't print any redundant
information.
3) When printing MIR, don't print any redundant information.
I'd like to change 2) to:
2) When -debug-printing a MF entirely, don't omit any redundant information.
Differential Revision: https://reviews.llvm.org/D43337
Modified:
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineFunction.cpp
llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll
llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll
llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=326094&r1=326093&r2=326094&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Mon Feb 26 07:23:42 2018
@@ -328,7 +328,7 @@ void MachineBasicBlock::print(raw_ostrea
bool HasLineAttributes = false;
// Print the preds of this block according to the CFG.
- if (!pred_empty()) {
+ if (!pred_empty() && IsStandalone) {
if (Indexes) OS << '\t';
// Don't indent(2), align with previous line attributes.
OS << "; predecessors: ";
@@ -354,7 +354,7 @@ void MachineBasicBlock::print(raw_ostrea
<< format("0x%08" PRIx32, getSuccProbability(I).getNumerator())
<< ')';
}
- if (!Probs.empty()) {
+ if (!Probs.empty() && IsStandalone) {
// Print human readable probabilities as comments.
OS << "; ";
for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
@@ -419,7 +419,7 @@ void MachineBasicBlock::print(raw_ostrea
if (IsInBundle)
OS.indent(2) << "}\n";
- if (IrrLoopHeaderWeight) {
+ if (IrrLoopHeaderWeight && IsStandalone) {
if (Indexes) OS << '\t';
OS.indent(2) << "; Irreducible loop header weight: "
<< IrrLoopHeaderWeight.getValue() << '\n';
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=326094&r1=326093&r2=326094&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Feb 26 07:23:42 2018
@@ -522,9 +522,8 @@ void MachineFunction::print(raw_ostream
MST.incorporateFunction(getFunction());
for (const auto &BB : *this) {
OS << '\n';
- // If we print the whole function, don't print any verbose information,
- // since that information is already present.
- BB.print(OS, MST, Indexes, /*IsStandalone=*/false);
+ // If we print the whole function, print it at its most verbose level.
+ BB.print(OS, MST, Indexes, /*IsStandalone=*/true);
}
OS << "\n# End machine code for function " << getName() << ".\n\n";
Modified: llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll?rev=326094&r1=326093&r2=326094&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll Mon Feb 26 07:23:42 2018
@@ -29,7 +29,7 @@ declare void @callee2(i8*, i8*, i8*, i8*
; CHECK: [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
; CHECK: [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
; CHECK: STRXui %{{.*}}, %fixed-stack.0
-; CHECK: STRXui [[VRB]], %fixed-stack.1
+; CHECK: STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
; Make sure that there is an dependence edge between fi#-2 and fi#-4.
; Without this edge the scheduler would be free to move the store accross the load.
Modified: llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll?rev=326094&r1=326093&r2=326094&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/Windows/dbzchk.ll Mon Feb 26 07:23:42 2018
@@ -119,7 +119,7 @@ attributes #0 = { optsize }
; CHECK-CFG-DAG: t2B %bb.3
; CHECK-CFG-DAG: %bb.2
-; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}, 0
+; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}{{[^,]*}}, 0
; CHECK-CFG-DAG: t2Bcc %bb.5
; CHECK-CFG-DAG: %bb.4
Modified: llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll?rev=326094&r1=326093&r2=326094&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/post-inc-aa-metadata.ll Mon Feb 26 07:23:42 2018
@@ -3,7 +3,7 @@
; Check that the generated post-increment load has TBAA information.
; CHECK-LABEL: Machine code for function fred:
-; CHECK: = V6_vL32b_pi %{{[0-9]+}}, 64; mem:LD64[{{.*}}](tbaa=
+; CHECK: = V6_vL32b_pi %{{[0-9]+}}{{[^,]*}}, 64; mem:LD64[{{.*}}](tbaa=
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll?rev=326094&r1=326093&r2=326094&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll Mon Feb 26 07:23:42 2018
@@ -42,7 +42,7 @@ bar:
; CHECK-LABEL: fn3
define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def $cr0
+; CHECK: ANDIo killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0
; CHECK: BCC 76, killed [[CREG]]
%1 = and i32 %a, 10
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