[PATCH] D42203: [AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader
Tim Renouf via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 26 06:49:56 PST 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL326088: [AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader (authored by tpr, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D42203?vs=133031&id=135896#toc
Repository:
rL LLVM
https://reviews.llvm.org/D42203
Files:
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/trunk/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
Index: llvm/trunk/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
@@ -0,0 +1,34 @@
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
+
+; On gfx9 and later, a HS is a merged shader, in which s0-s7 are reserved by the
+; hardware, so the PAL puts the GIT (global information table) in s8 rather
+; than s0.
+
+; GCN-LABEL: {{^}}_amdgpu_hs_main:
+; GCN: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]:
+; PREGFX9: s_mov_b32 s[[GITPTR]], s0
+; GFX9: s_mov_b32 s[[GITPTR]], s8
+
+define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 inreg %arg7, <6 x i32> inreg %arg8) {
+.entry:
+ %__llpc_global_proxy_7.i = alloca [3 x <4 x float>], align 16, addrspace(5)
+ %tmp = icmp ult i32 undef, undef
+ br i1 %tmp, label %.beginls, label %.endls
+
+.beginls: ; preds = %.entry
+ %tmp15 = extractelement <6 x i32> %arg8, i32 3
+ %.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
+ %.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
+ %tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
+ br label %.endls
+
+.endls: ; preds = %.beginls, %.entry
+ %.fca.2.gep120.i = getelementptr inbounds [3 x <4 x float>], [3 x <4 x float>] addrspace(5)* %__llpc_global_proxy_7.i, i64 0, i64 2
+ store <4 x float> <float 9.000000e+00, float 1.000000e+01, float 1.100000e+01, float 1.200000e+01>, <4 x float> addrspace(5)* %.fca.2.gep120.i, align 16
+ br label %bb
+
+bb: ; preds = %bb, %.endls
+ %lsr.iv182 = phi [3 x <4 x float>] addrspace(5)* [ undef, %bb ], [ %__llpc_global_proxy_7.i, %.endls ]
+ %scevgep183 = getelementptr [3 x <4 x float>], [3 x <4 x float>] addrspace(5)* %lsr.iv182, i32 0, i32 1
+ br label %bb
+}
Index: llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -387,8 +387,21 @@
const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64);
BuildMI(MBB, I, DL, GetPC64, Rsrc01);
}
+ auto GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
+ if (ST.hasMergedShaders()) {
+ switch (MF.getFunction().getCallingConv()) {
+ case CallingConv::AMDGPU_HS:
+ case CallingConv::AMDGPU_GS:
+ // Low GIT address is passed in s8 rather than s0 for an LS+HS or
+ // ES+GS merged shader on gfx9+.
+ GitPtrLo = AMDGPU::SGPR8;
+ break;
+ default:
+ break;
+ }
+ }
BuildMI(MBB, I, DL, SMovB32, RsrcLo)
- .addReg(AMDGPU::SGPR0) // Low address passed in
+ .addReg(GitPtrLo)
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
// We now have the GIT ptr - now get the scratch descriptor from the entry
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -845,6 +845,12 @@
return getGeneration() >= GFX9;
}
+ /// \returns true if the machine has merged shaders in which s0-s7 are
+ /// reserved by the hardware and user SGPRs start at s8
+ bool hasMergedShaders() const {
+ return getGeneration() >= GFX9;
+ }
+
/// \returns SGPR allocation granularity supported by the subtarget.
unsigned getSGPRAllocGranule() const {
return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
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