[llvm] r326043 - [TargetLowering] SimplifyDemandedVectorElts - pass demanded elts through TRUNCATE ops

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Feb 24 11:28:34 2018
New Revision: 326043

URL: http://llvm.org/viewvc/llvm-project?rev=326043&view=rev
Log:
[TargetLowering] SimplifyDemandedVectorElts - pass demanded elts through TRUNCATE ops

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/test/CodeGen/X86/vector-trunc.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=326043&r1=326042&r2=326043&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Feb 24 11:28:34 2018
@@ -1536,6 +1536,11 @@ bool TargetLowering::SimplifyDemandedVec
     }
     break;
   }
+  case ISD::TRUNCATE:
+    if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
+                                   KnownZero, TLO, Depth + 1))
+      return true;
+    break;
   default: {
     if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
       if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,

Modified: llvm/trunk/test/CodeGen/X86/vector-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-trunc.ll?rev=326043&r1=326042&r2=326043&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-trunc.ll Sat Feb 24 11:28:34 2018
@@ -1869,28 +1869,11 @@ entry:
 }
 
 define <8 x i16> @PR32160(<8 x i32> %x) {
-; SSE2-LABEL: PR32160:
-; SSE2:       # %bb.0:
-; SSE2-NEXT:    pslld $16, %xmm1
-; SSE2-NEXT:    psrad $16, %xmm1
-; SSE2-NEXT:    pslld $16, %xmm0
-; SSE2-NEXT:    psrad $16, %xmm0
-; SSE2-NEXT:    packssdw %xmm1, %xmm0
-; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[2,2,2,3,4,5,6,7]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; SSE2-NEXT:    retq
-;
-; SSSE3-LABEL: PR32160:
-; SSSE3:       # %bb.0:
-; SSSE3-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
-; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
-; SSSE3-NEXT:    retq
-;
-; SSE41-LABEL: PR32160:
-; SSE41:       # %bb.0:
-; SSE41-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
-; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
-; SSE41-NEXT:    retq
+; SSE-LABEL: PR32160:
+; SSE:       # %bb.0:
+; SSE-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,7]
+; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
+; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: PR32160:
 ; AVX1:       # %bb.0: