[PATCH] D43699: [AMDGPU] Shrinking V_SUBBREV_U32

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: kzhuravl, msearles.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, arsenm.

V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when
we try to commute V_SUBB_U32 in order to shrink it we do not then
process V_SUBBREV_U32 and it stay VOP3. This is fixed.


https://reviews.llvm.org/D43699

Files:
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  test/CodeGen/AMDGPU/combine-cond-add-sub.ll
  test/CodeGen/AMDGPU/shrink-carry.mir


Index: test/CodeGen/AMDGPU/shrink-carry.mir
===================================================================
--- test/CodeGen/AMDGPU/shrink-carry.mir
+++ test/CodeGen/AMDGPU/shrink-carry.mir
@@ -1,7 +1,7 @@
 # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: subbrev{{$}}
-# GCN:       V_SUBBREV_U32_e64 0, undef $vgpr0, killed $vcc, implicit $exec
+# GCN:       V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
 
 ---
 name:            subbrev
@@ -25,7 +25,7 @@
 ...
 
 # GCN-LABEL: name: subb{{$}}
-# GCN:       V_SUBB_U32_e64 undef $vgpr0, 0, killed $vcc, implicit $exec
+# GCN:       V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
 
 ---
 name:            subb
Index: test/CodeGen/AMDGPU/combine-cond-add-sub.ll
===================================================================
--- test/CodeGen/AMDGPU/combine-cond-add-sub.ll
+++ test/CodeGen/AMDGPU/combine-cond-add-sub.ll
@@ -19,8 +19,8 @@
 }
 
 ; GCN-LABEL: {{^}}sub1:
-; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
-; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, 0, [[CC]]
+; GCN: v_cmp_gt_u32_e32 vcc, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ; GCN-NOT: v_cndmask
 
 define amdgpu_kernel void @sub1(i32 addrspace(1)* nocapture %arg) {
@@ -134,8 +134,8 @@
 }
 
 ; GCN-LABEL: {{^}}sext_flclass:
-; GCN: v_cmp_class_f32_e{{32|64}} [[CC:[^,]+]],
-; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, 0, [[CC]]
+; GCN: v_cmp_class_f32_e32 vcc,
+; GCN: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ; GCN-NOT: v_cndmask
 
 define amdgpu_kernel void @sext_flclass(i32 addrspace(1)* nocapture %arg, float %x) {
Index: lib/Target/AMDGPU/SIShrinkInstructions.cpp
===================================================================
--- lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -92,7 +92,8 @@
 
       case AMDGPU::V_ADDC_U32_e64:
       case AMDGPU::V_SUBB_U32_e64:
-        if (TII->getNamedOperand(MI, AMDGPU::OpName::src1)->isImm())
+      case AMDGPU::V_SUBBREV_U32_e64:
+        if (!isVGPR(TII->getNamedOperand(MI, AMDGPU::OpName::src1), TRI, MRI))
           return false;
         // Additional verification is needed for sdst/src2.
         return true;


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