[PATCH] D43042: [MachineOperand][Target] MachineOperand::isRenamable semantics changes

[Geoff Berry via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL325931: [MachineOperand][Target] MachineOperand::isRenamable semantics changes (authored by gberry, committed by ).

Repository:
  rL LLVM

https://reviews.llvm.org/D43042

Files:
  llvm/trunk/include/llvm/CodeGen/MachineInstr.h
  llvm/trunk/include/llvm/CodeGen/MachineOperand.h
  llvm/trunk/include/llvm/Target/Target.td
  llvm/trunk/lib/CodeGen/MachineInstr.cpp
  llvm/trunk/lib/CodeGen/MachineOperand.cpp
  llvm/trunk/lib/CodeGen/MachineVerifier.cpp
  llvm/trunk/lib/CodeGen/RegAllocFast.cpp
  llvm/trunk/lib/CodeGen/VirtRegMap.cpp
  llvm/trunk/lib/Target/AArch64/AArch64.td
  llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
  llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
  llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
  llvm/trunk/lib/Target/ARM/ARM.td
  llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
  llvm/trunk/lib/Target/Hexagon/Hexagon.td
  llvm/trunk/lib/Target/Hexagon/RDFCopy.cpp
  llvm/trunk/lib/Target/Mips/Mips.td
  llvm/trunk/lib/Target/PowerPC/PPC.td
  llvm/trunk/lib/Target/RISCV/RISCV.td
  llvm/trunk/lib/Target/Sparc/Sparc.td
  llvm/trunk/lib/Target/SystemZ/SystemZ.td
  llvm/trunk/lib/Target/X86/X86.td
  llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
  llvm/trunk/test/CodeGen/AMDGPU/postra-norename.mir
  llvm/trunk/utils/TableGen/CodeGenTarget.cpp
  llvm/trunk/utils/TableGen/CodeGenTarget.h
  llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp

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