[llvm] r325941 - Shrink various scheduling tables by using narrower types.
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 23 11:32:56 PST 2018
Author: d0k
Date: Fri Feb 23 11:32:56 2018
New Revision: 325941
URL: http://llvm.org/viewvc/llvm-project?rev=325941&view=rev
Log:
Shrink various scheduling tables by using narrower types.
16 bits ought to be enough for everyone. This shrinks clang by ~1MB.
Modified:
llvm/trunk/include/llvm/MC/MCInstrItineraries.h
llvm/trunk/include/llvm/MC/MCSchedule.h
llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
Modified: llvm/trunk/include/llvm/MC/MCInstrItineraries.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrItineraries.h?rev=325941&r1=325940&r2=325941&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInstrItineraries.h (original)
+++ llvm/trunk/include/llvm/MC/MCInstrItineraries.h Fri Feb 23 11:32:56 2018
@@ -94,11 +94,11 @@ struct InstrStage {
/// cycle in which operands are read and written.
///
struct InstrItinerary {
- int NumMicroOps; ///< # of micro-ops, -1 means it's variable
- unsigned FirstStage; ///< Index of first stage in itinerary
- unsigned LastStage; ///< Index of last + 1 stage in itinerary
- unsigned FirstOperandCycle; ///< Index of first operand rd/wr
- unsigned LastOperandCycle; ///< Index of last + 1 operand rd/wr
+ int16_t NumMicroOps; ///< # of micro-ops, -1 means it's variable
+ uint16_t FirstStage; ///< Index of first stage in itinerary
+ uint16_t LastStage; ///< Index of last + 1 stage in itinerary
+ uint16_t FirstOperandCycle; ///< Index of first operand rd/wr
+ uint16_t LastOperandCycle; ///< Index of last + 1 operand rd/wr
};
//===----------------------------------------------------------------------===//
@@ -125,8 +125,8 @@ public:
/// \brief Returns true if the index is for the end marker itinerary.
bool isEndMarker(unsigned ItinClassIndx) const {
- return ((Itineraries[ItinClassIndx].FirstStage == ~0U) &&
- (Itineraries[ItinClassIndx].LastStage == ~0U));
+ return ((Itineraries[ItinClassIndx].FirstStage == UINT16_MAX) &&
+ (Itineraries[ItinClassIndx].LastStage == UINT16_MAX));
}
/// \brief Return the first stage of the itinerary.
Modified: llvm/trunk/include/llvm/MC/MCSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSchedule.h?rev=325941&r1=325940&r2=325941&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSchedule.h (original)
+++ llvm/trunk/include/llvm/MC/MCSchedule.h Fri Feb 23 11:32:56 2018
@@ -58,8 +58,8 @@ struct MCProcResourceDesc {
/// Identify one of the processor resource kinds consumed by a particular
/// scheduling class for the specified number of cycles.
struct MCWriteProcResEntry {
- unsigned ProcResourceIdx;
- unsigned Cycles;
+ uint16_t ProcResourceIdx;
+ uint16_t Cycles;
bool operator==(const MCWriteProcResEntry &Other) const {
return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
@@ -72,8 +72,8 @@ struct MCWriteProcResEntry {
/// the WriteResources of this def. When the operand expands to a sequence of
/// writes, this ID is the last write in the sequence.
struct MCWriteLatencyEntry {
- int Cycles;
- unsigned WriteResourceID;
+ int16_t Cycles;
+ uint16_t WriteResourceID;
bool operator==(const MCWriteLatencyEntry &Other) const {
return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
@@ -104,21 +104,21 @@ struct MCReadAdvanceEntry {
///
/// Defined as an aggregate struct for creating tables with initializer lists.
struct MCSchedClassDesc {
- static const unsigned short InvalidNumMicroOps = UINT16_MAX;
- static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
+ static const unsigned short InvalidNumMicroOps = (1U << 14) - 1;
+ static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
const char* Name;
#endif
- unsigned short NumMicroOps;
- bool BeginGroup;
- bool EndGroup;
- unsigned WriteProcResIdx; // First index into WriteProcResTable.
- unsigned NumWriteProcResEntries;
- unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
- unsigned NumWriteLatencyEntries;
- unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.
- unsigned NumReadAdvanceEntries;
+ uint16_t NumMicroOps : 14;
+ bool BeginGroup : 1;
+ bool EndGroup : 1;
+ uint16_t WriteProcResIdx; // First index into WriteProcResTable.
+ uint16_t NumWriteProcResEntries;
+ uint16_t WriteLatencyIdx; // First index into WriteLatencyTable.
+ uint16_t NumWriteLatencyEntries;
+ uint16_t ReadAdvanceIdx; // First index into ReadAdvanceTable.
+ uint16_t NumReadAdvanceEntries;
bool isValid() const {
return NumMicroOps != InvalidNumMicroOps;
Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=325941&r1=325940&r2=325941&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Fri Feb 23 11:32:56 2018
@@ -209,7 +209,7 @@ static int getLatency(LLVMDisasmContext
return NoInformationAvailable;
// Compute output latency.
- int Latency = 0;
+ int16_t Latency = 0;
for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
DefIdx != DefEnd; ++DefIdx) {
// Lookup the definition's write latency in SubtargetInfo.
Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=325941&r1=325940&r2=325941&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Fri Feb 23 11:32:56 2018
@@ -444,7 +444,7 @@ EmitStageAndOperandCycleData(raw_ostream
}
// Check to see if stage already exists and create if it doesn't
- unsigned FindStage = 0;
+ uint16_t FindStage = 0;
if (NStages > 0) {
FindStage = ItinStageMap[ItinStageString];
if (FindStage == 0) {
@@ -460,7 +460,7 @@ EmitStageAndOperandCycleData(raw_ostream
}
// Check to see if operand cycle already exists and create if it doesn't
- unsigned FindOperandCycle = 0;
+ uint16_t FindOperandCycle = 0;
if (NOperandCycles > 0) {
std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
FindOperandCycle = ItinOperandMap[ItinOperandString];
@@ -482,10 +482,14 @@ EmitStageAndOperandCycleData(raw_ostream
}
// Set up itinerary as location and location + stage count
- int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
- InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
- FindOperandCycle,
- FindOperandCycle + NOperandCycles };
+ int16_t NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
+ InstrItinerary Intinerary = {
+ NumUOps,
+ FindStage,
+ uint16_t(FindStage + NStages),
+ FindOperandCycle,
+ uint16_t(FindOperandCycle + NOperandCycles),
+ };
// Inject - empty slots will be 0, 0
ItinList[SchedClassIdx] = Intinerary;
@@ -561,7 +565,8 @@ EmitItineraries(raw_ostream &OS,
", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
}
// End processor itinerary table
- OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
+ OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
+ "// end marker\n";
OS << "};\n";
}
}
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