[PATCH] D43682: [mips] Support 'z' inline asm constraint

[Simon Atanasyan via Phabricator via llvm-commits]

atanasyan created this revision.
atanasyan added a reviewer: sdardis.
Herald added subscribers: eraman, arichardson.

The 'z' constraint is used to deal with the floating-point condition code register. Using this constraint the following short, although useless piece of code

  float a = 1.0, b = 2.0;
  int res;
  __asm__ __volatile__(
         "c.eq.s %1,%2"
     : "+z" (res) : "f" (a), "f" (a) : );

translated to this series of assembler commands

  ctc1    $1, $fcc0
  c.eq.s  $f2, $f0
  cfc1    $1, $fcc0

So we can read/write the floating-point condition code register from/to a variable.

This patch adds support for the 'z' constraint on LLVM level only. One more fix is required to support the constraint in the Clang.


Repository:
  rL LLVM

https://reviews.llvm.org/D43682

Files:
  lib/Target/Mips/MipsISelLowering.cpp
  lib/Target/Mips/MipsSEInstrInfo.cpp
  test/CodeGen/Mips/inlineasm_constraint_z.ll


Index: test/CodeGen/Mips/inlineasm_constraint_z.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/inlineasm_constraint_z.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=mips < %s | FileCheck %s
+
+define void @foo() {
+entry:
+; CHECK-LABEL: foo:
+
+  %a = alloca i32, align 4
+  %0 = load i32, i32* %a, align 4
+
+  %1 = call i32 asm sideeffect "c.eq.s $1,$2", "=z,f,f,0,~{$1}"(float 1.0, float 2.0, i32 %0)
+; CHECK: ctc1    $[[R:[0-9]+]], $fcc0
+; CHECK: c.eq.s  $f0, $f1
+; CHECK: cfc1    $[[R]], $fcc0
+
+  store i32 %1, i32* %a, align 4
+  ret void
+}
Index: lib/Target/Mips/MipsSEInstrInfo.cpp
===================================================================
--- lib/Target/Mips/MipsSEInstrInfo.cpp
+++ lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -103,6 +103,8 @@
       Opc = Mips::MFHI_DSP;
     else if (Mips::LO32DSPRegClass.contains(SrcReg))
       Opc = Mips::MFLO_DSP;
+    else if (Mips::FCCRegClass.contains(SrcReg))
+      Opc = Mips::CFC1;
     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
@@ -124,6 +126,8 @@
       Opc = Mips::MTHI_DSP;
     else if (Mips::LO32DSPRegClass.contains(DestReg))
       Opc = Mips::MTLO_DSP;
+    else if (Mips::FCCRegClass.contains(DestReg))
+      Opc = Mips::CTC1;
     else if (Mips::DSPCCRegClass.contains(DestReg)) {
       BuildMI(MBB, I, DL, get(Mips::WRDSP))
         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -3652,6 +3652,7 @@
       case 'c':
       case 'l':
       case 'x':
+      case 'z':
         return C_RegisterClass;
       case 'R':
         return C_Memory;
@@ -3697,6 +3698,7 @@
   case 'c': // $25 for indirect jumps
   case 'l': // lo register
   case 'x': // hilo register pair
+  case 'z': // FCSR
     if (type->isIntegerTy())
       weight = CW_SpecificReg;
     break;
@@ -3872,6 +3874,11 @@
       // Fixme: Not triggering the use of both hi and low
       // This will generate an error message
       return std::make_pair(0U, nullptr);
+    case 'z': // Use a floating-point condition code register.
+      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
+        return std::make_pair((unsigned)Mips::FCC0, &Mips::FCCRegClass);
+      // This will generate an error message
+      return std::make_pair(0U, nullptr);
     }
   }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D43682.135647.patch
Type: text/x-patch
Size: 2628 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180223/679a0446/attachment.bin>