[PATCH] D43553: TableGen: Add !size operation

[Artem Belevich via Phabricator via llvm-commits]

tra accepted this revision.
tra added inline comments.
This revision is now accepted and ready to land.


================
Comment at: test/TableGen/size.td:6-20
+// CHECK: def A1 {
+// CHECK:   int Val = 0;
+// CHECK: }
+
+// CHECK: def A2 {
+// CHECK:   int Val = 3;
+// CHECK: }
----------------
nhaehnle wrote:
> tra wrote:
> > I'd interleave those with the `def An:...` below.
> I'd prefer to leave it as-is. Unlike other tools, TableGen output is not in the order of the input file but sorted alphabetically, so I find interleaving the CHECK lines misleading. I think it's easier to work with this way.
OK. In this case your `def`s are also sorted, that's why I've suggested interleaving the checks. It's fine either way.


Repository:
  rL LLVM

https://reviews.llvm.org/D43553