[PATCH] D42834: [RISCV] Implement c.lui immedate operand constraint

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

Looks good to me now. I had a go at rewording the c_lui_imm comment - feel free to take from that suggestion if you think it's any clearer.



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Comment at: lib/Target/RISCV/RISCVInstrInfoC.td:51-54
+// c_lui_imm checks the immediate range in [1, 31] or [0xfffe0, 0xfffff].
+// The RISCV ISA describes the constraint as [1, 63] with signed extension
+// highest bit. Eventually, the upper value could represent will be [1, 31]
+// or [0xfffe0, 0xfffff], the value will encoded as [1, 63].
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I had a go at rewording - does this seem any clearer to you? It's hard to explain concisely.

c_lui_imm checks the immediate range is in [1, 31] or [0xfffe0, 0xfffff]. The RISC-V ISA describes the constraint as [1, 63], with that value being loaded in to bits 17-12 of the destination register and sign extended from bit 17. Therefore, this 6-bit immediate can represent values in the ranges [1, 31] and [0xfffe0, 0xfffff].


Repository:
  rL LLVM

https://reviews.llvm.org/D42834