[llvm] r325752 - [NFC] fix trivial typos in comments
Hiroshi Inoue via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 21 23:48:29 PST 2018
Author: inouehrs
Date: Wed Feb 21 23:48:29 2018
New Revision: 325752
URL: http://llvm.org/viewvc/llvm-project?rev=325752&view=rev
Log:
[NFC] fix trivial typos in comments
"a a" -> "a"
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/test/tools/llvm-xray/X86/extract-all-sledtypes.txt
llvm/trunk/tools/llvm-readobj/COFFDumper.cpp
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h?rev=325752&r1=325751&r2=325752&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h Wed Feb 21 23:48:29 2018
@@ -218,7 +218,7 @@ enum {
/// - InsnID - Instruction ID to modify
/// - RegNum - The register to add
GIR_AddRegister,
- /// Add a a temporary register to the specified instruction
+ /// Add a temporary register to the specified instruction
/// - InsnID - Instruction ID to modify
/// - TempRegID - The temporary register ID to add
GIR_AddTempRegister,
Modified: llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp?rev=325752&r1=325751&r2=325752&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp Wed Feb 21 23:48:29 2018
@@ -218,7 +218,7 @@ Counters SIInsertWaits::getHwCounts(Mach
unsigned Size = TRI->getRegSizeInBits(*RC);
Result.Named.LGKM = Size > 32 ? 2 : 1;
} else {
- // s_dcache_inv etc. do not have a a destination register. Assume we
+ // s_dcache_inv etc. do not have a destination register. Assume we
// want a wait on these.
// XXX - What is the right value?
Result.Named.LGKM = 1;
Modified: llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp?rev=325752&r1=325751&r2=325752&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp Wed Feb 21 23:48:29 2018
@@ -358,7 +358,7 @@ int ARMTTIImpl::getVectorInstrCost(unsig
int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
const Instruction *I) {
int ISD = TLI->InstructionOpcodeToISD(Opcode);
- // On NEON a a vector select gets lowered to vbsl.
+ // On NEON a vector select gets lowered to vbsl.
if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
// Lowering of some vector selects is currently far from perfect.
static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=325752&r1=325751&r2=325752&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Wed Feb 21 23:48:29 2018
@@ -1914,7 +1914,7 @@ void HexagonFrameLowering::determineCall
if (OptimizeSpillSlots && !isOptNone(MF))
optimizeSpillSlots(MF, NewRegs);
- // We need to reserve a a spill slot if scavenging could potentially require
+ // We need to reserve a spill slot if scavenging could potentially require
// spilling a scavenged register.
if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
MachineFrameInfo &MFI = MF.getFrameInfo();
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=325752&r1=325751&r2=325752&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Feb 21 23:48:29 2018
@@ -3885,7 +3885,7 @@ bool MipsAsmParser::expandCondBranches(M
// This is accomplished by using a BNEZ with the result of the SLT.
//
// The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT
- // and BLE with BGT), so we change the BNEZ into a a BEQZ.
+ // and BLE with BGT), so we change the BNEZ into a BEQZ.
// Because only BGE and BLE branch on equality, we can use the
// AcceptsEquality variable to decide when to emit the BEQZ.
// Note that the order of the SLT arguments doesn't change between
Modified: llvm/trunk/test/tools/llvm-xray/X86/extract-all-sledtypes.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-xray/X86/extract-all-sledtypes.txt?rev=325752&r1=325751&r2=325752&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-xray/X86/extract-all-sledtypes.txt (original)
+++ llvm/trunk/test/tools/llvm-xray/X86/extract-all-sledtypes.txt Wed Feb 21 23:48:29 2018
@@ -1,5 +1,5 @@
# Test that we can extract all the sled types we know about. This is built with
-# a a file with functions always instrumented, and using the built-ins and
+# a file with functions always instrumented, and using the built-ins and
# intrinsics supported by clang. Those are built with:
#
# clang++ -c all-sleds.cc -o all-sleds.o -fpic -std=c++11 -fxray-instrument
Modified: llvm/trunk/tools/llvm-readobj/COFFDumper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-readobj/COFFDumper.cpp?rev=325752&r1=325751&r2=325752&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-readobj/COFFDumper.cpp (original)
+++ llvm/trunk/tools/llvm-readobj/COFFDumper.cpp Wed Feb 21 23:48:29 2018
@@ -244,7 +244,7 @@ std::error_code createCOFFDumper(const o
} // namespace llvm
-// Given a a section and an offset into this section the function returns the
+// Given a section and an offset into this section the function returns the
// symbol used for the relocation at the offset.
std::error_code COFFDumper::resolveSymbol(const coff_section *Section,
uint64_t Offset, SymbolRef &Sym) {
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