[llvm] r325697 - [Hexagon] Return true in enableMultipleCopyHints().

[Jonas Paulsson via llvm-commits]

Author: jonpa
Date: Wed Feb 21 08:37:45 2018
New Revision: 325697

URL: http://llvm.org/viewvc/llvm-project?rev=325697&view=rev
Log:
[Hexagon]  Return true in enableMultipleCopyHints().

Enable multiple COPY hints to eliminate more COPYs during register allocation.

Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.

Review: Krzysztof Parzyszek

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
    llvm/trunk/test/CodeGen/Hexagon/autohvx/reg-sequence.ll
    llvm/trunk/test/CodeGen/Hexagon/mul64-sext.ll
    llvm/trunk/test/CodeGen/Hexagon/pred-absolute-store.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h?rev=325697&r1=325696&r2=325697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h Wed Feb 21 08:37:45 2018
@@ -39,6 +39,8 @@ public:
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
+  bool enableMultipleCopyHints() const override { return true; }
+
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
         unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
 

Modified: llvm/trunk/test/CodeGen/Hexagon/autohvx/reg-sequence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/reg-sequence.ll?rev=325697&r1=325696&r2=325697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/reg-sequence.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/reg-sequence.ll Wed Feb 21 08:37:45 2018
@@ -99,8 +99,8 @@ b2:
 }
 
 ; CHECK-LABEL: test_22:
-; CHECK: v3 = v2
 ; CHECK: vcombine(v3,v2)
+; CHECK: v1 = v0
 ; Result: v1:0 = vcombine(v2,v2)
 define <128 x i8> @test_22(<128 x i8> %a0, <128 x i8> %a1) #0 {
 b2:
@@ -145,8 +145,8 @@ b2:
 }
 
 ; CHECK-LABEL: test_33:
-; CHECK: v2 = v3
 ; CHECK: vcombine(v3,v2)
+; CHECK: v0 = v1
 ; Result: v1:0 = vcombine(v3,v3)
 define <128 x i8> @test_33(<128 x i8> %a0, <128 x i8> %a1) #0 {
 b2:

Modified: llvm/trunk/test/CodeGen/Hexagon/mul64-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/mul64-sext.ll?rev=325697&r1=325696&r2=325697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/mul64-sext.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/mul64-sext.ll Wed Feb 21 08:37:45 2018
@@ -75,9 +75,9 @@ b3:
 }
 
 ; CHECK-LABEL: mul_nac_2
-; CHECK: r0 = memw(r0+#0)
-; CHECK: r5:4 -= mpy(r2,r0)
 ; CHECK: r1:0 = combine(r5,r4)
+; CHECK: r6 = memw(r0+#0)
+; CHECK: r1:0 -= mpy(r2,r6)
 ; CHECK: jumpr r31
 define i64 @mul_nac_2(i32* %a0, i64 %a1, i64 %a2) #0 {
 b3:

Modified: llvm/trunk/test/CodeGen/Hexagon/pred-absolute-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/pred-absolute-store.ll?rev=325697&r1=325696&r2=325697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/pred-absolute-store.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/pred-absolute-store.ll Wed Feb 21 08:37:45 2018
@@ -1,7 +1,7 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we are able to predicate instructions with absolute
 ; addressing mode.
-; CHECK: if ({{!?}}p{{[0-3]}}) memw(##gvar) = r{{[0-9]+}}
+; CHECK: if ({{!?}}p{{[0-3]}}.new) memw(##gvar) = r{{[0-9]+}}
 
 @gvar = external global i32
 define i32 @test2(i32 %a, i32 %b) nounwind {