[PATCH] D43531: [X86] Turn setne X, signedmin into setgt X, signedmin in LowerVSETCC to avoid an invert

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.

This will fix one of the regressions from https://reviews.llvm.org/D42948.


https://reviews.llvm.org/D43531

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vector-compare-simplify.ll


Index: test/CodeGen/X86/vector-compare-simplify.ll
===================================================================
--- test/CodeGen/X86/vector-compare-simplify.ll
+++ test/CodeGen/X86/vector-compare-simplify.ll
@@ -334,3 +334,14 @@
   ret <4 x i32> %r
 }
 
+; Make sure we can efficiently handle ne smin by turning into sgt.
+define <4 x i32> @ne_smin(<4 x i32> %x) {
+; CHECK-LABEL: ne_smin:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcmpgtd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %cmp = icmp ne <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+  %r = sext <4 x i1> %cmp to <4 x i32>
+  ret <4 x i32> %r
+}
+
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -18054,6 +18054,15 @@
     }
   }
 
+  // If this is a SETNE against the signed minimum value, change it to SETGT.
+  // Otherwise we use PCMPEQ+invert.
+  APInt ConstValue;
+  if (Cond == ISD::SETNE &&
+      ISD::isConstantSplatVector(Op1.getNode(), ConstValue),
+      ConstValue.isMinSignedValue()) {
+    Cond = ISD::SETGT;
+  }
+
   // If both operands are known non-negative, then an unsigned compare is the
   // same as a signed compare and there's no need to flip signbits.
   // TODO: We could check for more general simplifications here since we're


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