[llvm] r325616 - [ARM] Lower BR_CC for f16

[Sjoerd Meijer via llvm-commits]

Author: sjoerdmeijer
Date: Tue Feb 20 11:28:05 2018
New Revision: 325616

URL: http://llvm.org/viewvc/llvm-project?rev=325616&view=rev
Log:
[ARM] Lower BR_CC for f16

This case wasn't handled yet.

Differential Revision: https://reviews.llvm.org/D43508


Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=325616&r1=325615&r2=325616&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 20 11:28:05 2018
@@ -1058,6 +1058,7 @@ ARMTargetLowering::ARMTargetLowering(con
 
   setOperationAction(ISD::BRCOND,    MVT::Other, Custom);
   setOperationAction(ISD::BR_CC,     MVT::i32,   Custom);
+  setOperationAction(ISD::BR_CC,     MVT::f16,   Custom);
   setOperationAction(ISD::BR_CC,     MVT::f32,   Custom);
   setOperationAction(ISD::BR_CC,     MVT::f64,   Custom);
   setOperationAction(ISD::BR_JT,     MVT::Other, Custom);
@@ -4688,8 +4689,6 @@ SDValue ARMTargetLowering::LowerBR_CC(SD
                        Chain, Dest, ARMcc, CCR, Cmp);
   }
 
-  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
-
   if (getTargetMachine().Options.UnsafeFPMath &&
       (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
        CC == ISD::SETNE || CC == ISD::SETUNE)) {

Modified: llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll?rev=325616&r1=325615&r2=325616&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll Tue Feb 20 11:28:05 2018
@@ -136,7 +136,7 @@ entry:
   %0 = bitcast float %F.coerce to i32
   %tmp.0.extract.trunc = trunc i32 %0 to i16
   %1 = bitcast i16 %tmp.0.extract.trunc to half
-  %cmp = fcmp une half %1, 0.000000e+00 
+  %cmp = fcmp une half %1, 0.000000e+00
   ret i1 %cmp
 
 ; CHECK-LABEL:             VCMP2:
@@ -185,6 +185,36 @@ entry:
 ; CHECK-HARDFP-FULLFP16:   vcmpe.f16 s{{.}}, s{{.}}
 }
 
+; Test lowering of BR_CC
+define hidden i32 @VCMPBRCC() {
+entry:
+  %f = alloca half, align 2
+  br label %for.cond
+
+for.cond:
+  %0 = load half, half* %f, align 2
+  %cmp = fcmp nnan ninf nsz ole half %0, 0xH6800
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:
+  ret i32 1
+
+for.end:
+  ret i32 0
+
+; CHECK-LABEL:            VCMPBRCC:
+
+; CHECK-SOFT:             bl  __aeabi_fcmple
+; CHECK-SOFT:             cmp r0, #0
+
+; CHECK-SOFTFP-FP16:      vcvtb.f32.f16 [[S2:s[0-9]]], [[S2]]
+; CHECK-SOFTFP-FP16:      vcmpe.f32 [[S2]], s0
+; CHECK-SOFTFP-FP16:      vmrs  APSR_nzcv, fpscr
+
+; CHECK-SOFTFP-FULLFP16:  vcmpe.f16 s{{.}}, s{{.}}
+; CHECK-SOFTFP-FULLFP16:  vmrs  APSR_nzcv, fpscr
+}
+
 ; 5. VCVT (between floating-point and fixed-point)
 ; Only assembly/disassembly support