[llvm] r325606 - [Hexagon] Handle *Low8 register classes in early if-conversion

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 20 10:19:17 PST 2018


Author: kparzysz
Date: Tue Feb 20 10:19:17 2018
New Revision: 325606

URL: http://llvm.org/viewvc/llvm-project?rev=325606&view=rev
Log:
[Hexagon] Handle *Low8 register classes in early if-conversion

Added:
    llvm/trunk/test/CodeGen/Hexagon/early-if-low8.mir
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=325606&r1=325605&r2=325606&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Tue Feb 20 10:19:17 2018
@@ -765,9 +765,11 @@ unsigned HexagonEarlyIfConversion::build
   unsigned Opc = 0;
   switch (DRC->getID()) {
     case Hexagon::IntRegsRegClassID:
+    case Hexagon::IntRegsLow8RegClassID:
       Opc = Hexagon::C2_mux;
       break;
     case Hexagon::DoubleRegsRegClassID:
+    case Hexagon::GeneralDoubleLow8RegsRegClassID:
       Opc = Hexagon::PS_pselect;
       break;
     case Hexagon::HvxVRRegClassID:

Added: llvm/trunk/test/CodeGen/Hexagon/early-if-low8.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-low8.mir?rev=325606&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/early-if-low8.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/early-if-low8.mir Tue Feb 20 10:19:17 2018
@@ -0,0 +1,27 @@
+# RUN: llc -march=hexagon -run-pass hexagon-early-if %s -o - | FileCheck %s
+
+# Make sure that early if-conversion handles the *low8 register classes:
+# CHECK: intregslow8 = C2_mux
+# CHECK: generaldoublelow8regs = PS_pselect
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $r0, $r1
+    %0:intregslow8 = COPY $r0
+    %1:intregslow8 = COPY $r1
+    %2:generaldoublelow8regs = A2_tfrpi 1
+    %3:predregs = C2_cmpeq %0, %1
+    J2_jumpf %3, %bb.2, implicit-def $pc
+  bb.1:
+    %4:intregslow8 = A2_addi %0, 1
+    %5:generaldoublelow8regs = A2_tfrpi 0
+  bb.2:
+    %6:intregslow8 = PHI %0, %bb.0, %4, %bb.1
+    %7:generaldoublelow8regs = PHI %2, %bb.0, %5, %bb.1
+    $r0 = COPY %6
+    $d1 = COPY %7
+    J2_jumpr $r31, implicit $r0, implicit $d1, implicit-def $pc
+...




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