[PATCH] D43460: [X86] Fix scheduling info for IMUL on haswell onwards.

[Clement Courbet via Phabricator via llvm-commits]

courbet added a comment.

In https://reviews.llvm.org/D43460#1012088, @courbet wrote:

> In https://reviews.llvm.org/D43460#1012087, @RKSimon wrote:
>
> > @craig.topper mentioned that IMUL support is missing from SandyBridge as well (PR36084)
>
>
> I'll try to put my hands on a sandybridge and run the tool there.


I've run the tool on `snb`:

- IMUL32*, IMUL16rr and IMUL8r use 1xP1
- IMUL16rri8 uses 1xP1 + 1xP015
- We don't handle IMUL16rri because the 16-bit value results in an LCP stall, but I will assume it's similar to IMUL16rri8

I'll udpate the diff with the results.


Repository:
  rL LLVM

https://reviews.llvm.org/D43460