[PATCH] D43283: Variable register class using HwMode

[Aleksandar Beserminji via Phabricator via llvm-commits]

abeserminji added a comment.

In my particular example for Mips I have a situation like this:

def AFGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u", 0, 15)>;
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
def VarFGR64 : RegisterClassByHwMode<[DefaultMode, HwMips64], [AFGR64, FGR64]>, RegisterClass<"Mips", [f64], 64, (add D0)>;

Where AFGR64 and FGR64 would represent DefaultRegClass and FP64RegClass. 
Until now I didn't experience any problems with wrong offsets being calculated, but maybe I'm missing something here?


Repository:
  rL LLVM

https://reviews.llvm.org/D43283