[PATCH] D43441: [X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32-bit targets (PR31630)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Why a DAG combine and not Custom type legalization?



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Comment at: lib/Target/X86/X86ISelLowering.cpp:37030
+  // Attempt AVX512-only combines.
+  if (Subtarget.hasAVX512())
+    if (SDValue Cvt = combineIntToFP_AVX512(N, DAG, Subtarget))
----------------
Why bother with the AVX512 check here if we're just going to check DQI inside?


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:37057
+  SDValue InVec =
+      DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecInVT,
+                  getZeroVector(VecInVT, Subtarget, DAG, DL), Op0, ZeroIdx);
----------------
Do we need the zeros or could this be scalar_to_vector?


Repository:
  rL LLVM

https://reviews.llvm.org/D43441