[llvm] r325462 - [AArch64][GlobalISel] Support G_INSERT/G_EXTRACT of types < s32 bits.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 18 09:03:03 PST 2018
Author: aemerson
Date: Sun Feb 18 09:03:02 2018
New Revision: 325462
URL: http://llvm.org/viewvc/llvm-project?rev=325462&view=rev
Log:
[AArch64][GlobalISel] Support G_INSERT/G_EXTRACT of types < s32 bits.
These are needed for operations on fp16 types in a later patch.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=325462&r1=325461&r2=325462&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Sun Feb 18 09:03:02 2018
@@ -789,15 +789,23 @@ bool AArch64InstructionSelector::select(
}
case TargetOpcode::G_EXTRACT: {
LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
+ LLT DstTy = MRI.getType(I.getOperand(0).getReg());
+ unsigned SrcSize = SrcTy.getSizeInBits();
// Larger extracts are vectors, same-size extracts should be something else
// by now (either split up or simplified to a COPY).
if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32)
return false;
- I.setDesc(TII.get(AArch64::UBFMXri));
+ I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri));
MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
Ty.getSizeInBits() - 1);
+ if (SrcSize < 64) {
+ assert(SrcSize == 32 && DstTy.getSizeInBits() == 16 &&
+ "unexpected G_EXTRACT types");
+ return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ }
+
unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
TII.get(AArch64::COPY))
@@ -812,17 +820,25 @@ bool AArch64InstructionSelector::select(
case TargetOpcode::G_INSERT: {
LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
+ LLT DstTy = MRI.getType(I.getOperand(0).getReg());
+ unsigned DstSize = DstTy.getSizeInBits();
// Larger inserts are vectors, same-size ones should be something else by
// now (split up or turned into COPYs).
if (Ty.getSizeInBits() > 64 || SrcTy.getSizeInBits() > 32)
return false;
- I.setDesc(TII.get(AArch64::BFMXri));
+ I.setDesc(TII.get(DstSize == 64 ? AArch64::BFMXri : AArch64::BFMWri));
unsigned LSB = I.getOperand(3).getImm();
unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
- I.getOperand(3).setImm((64 - LSB) % 64);
+ I.getOperand(3).setImm((DstSize - LSB) % DstSize);
MachineInstrBuilder(MF, I).addImm(Width - 1);
+ if (DstSize < 64) {
+ assert(DstSize == 32 && SrcTy.getSizeInBits() == 16 &&
+ "unexpected G_INSERT types");
+ return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ }
+
unsigned SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
BuildMI(MBB, I.getIterator(), I.getDebugLoc(),
TII.get(AArch64::SUBREG_TO_REG))
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir?rev=325462&r1=325461&r2=325462&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir Sun Feb 18 09:03:02 2018
@@ -1,8 +1,8 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
---
-# CHECK-LABEL: name: insert_gprs
-name: insert_gprs
+name: insert_gprx
legalized: true
regBankSelected: true
@@ -10,26 +10,54 @@ body: |
bb.0:
liveins: $x0
+ ; CHECK-LABEL: name: insert_gprx
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
+ ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+ ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG]], 0, 31
+ ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+ ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 51, 31
+ ; CHECK: $x0 = COPY [[BFMXri]]
+ ; CHECK: $x1 = COPY [[BFMXri1]]
%0:gpr(s32) = COPY $w0
%1:gpr(s64) = G_IMPLICIT_DEF
- ; CHECK: body:
- ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
- ; CHECK: %2:gpr64 = BFMXri %1, [[TMP]], 0, 31
%2:gpr(s64) = G_INSERT %1, %0, 0
- ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
- ; CHECK: %3:gpr64 = BFMXri %1, [[TMP]], 51, 31
%3:gpr(s64) = G_INSERT %1, %0, 13
$x0 = COPY %2
$x1 = COPY %3
...
+---
+name: insert_gprw
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $w0, $w1
+ ; CHECK-LABEL: name: insert_gprw
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+ ; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY]], 0, 15
+ ; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY]], 16, 15
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[BFMWri1]]
+ ; CHECK: $w0 = COPY [[COPY1]]
+ %1:gpr(s32) = COPY $w0
+ %2:gpr(s32) = COPY $w1
+ %3:gpr(s16) = G_TRUNC %1(s32)
+ %4:gpr(s16) = G_TRUNC %1(s32)
+ %5:gpr(s32) = G_IMPLICIT_DEF
+ %6:gpr(s32) = G_INSERT %5, %3(s16), 0
+ %7:gpr(s32) = G_INSERT %6, %4(s16), 16
+ %0:gpr(s32) = COPY %7(s32)
+ $w0 = COPY %0
+...
---
-# CHECK-LABEL: name: extract_gprs
name: extract_gprs
legalized: true
regBankSelected: true
@@ -38,17 +66,45 @@ body: |
bb.0:
liveins: $x0
+ ; CHECK-LABEL: name: extract_gprs
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 0, 31
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[UBFMXri]].sub_32
+ ; CHECK: [[UBFMXri1:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 13, 44
+ ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[UBFMXri1]].sub_32
+ ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK: $w1 = COPY [[COPY2]]
%0:gpr(s64) = COPY $x0
- ; CHECK: body:
- ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 0, 31
- ; CHECK: %1:gpr32 = COPY [[TMP]].sub_32
%1:gpr(s32) = G_EXTRACT %0, 0
- ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 13, 44
- ; CHECK: %2:gpr32 = COPY [[TMP]].sub_32
%2:gpr(s32) = G_EXTRACT %0, 13
$w0 = COPY %1
$w1 = COPY %2
...
+
+---
+name: extract_gprw
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $w0
+
+ ; CHECK-LABEL: name: extract_gprw
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
+ ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 15, 30
+ ; CHECK: $h0 = COPY [[UBFMWri]]
+ ; CHECK: $h1 = COPY [[UBFMWri1]]
+ %0:gpr(s32) = COPY $w0
+
+ %1:gpr(s16) = G_EXTRACT %0, 0
+
+ %2:gpr(s16) = G_EXTRACT %0, 15
+
+ $h0 = COPY %1
+ $h1 = COPY %2
+...
More information about the llvm-commits
mailing list