[PATCH] D43374: [ARM]Decoding MSR with unpredictable destination register causes an assert

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:4247
+    }
+    unsigned SYSmvalue = Val & 0xFFF;
+    Parser.Lex(); 
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Shouldn't this be 0xFF as that's what you checked one line up?


https://reviews.llvm.org/D43374